WIFI design Guide based PW620-I 802.11b/g ----Hardware section Orin.Zhu August 31 st, 2007.

Slides:



Advertisements
Similar presentations
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
Advertisements

Device Drivers. Linux Device Drivers Linux supports three types of hardware device: character, block and network –character devices: R/W without buffering.
I/O and Networking Fred Kuhns
Dr. Rabie A. Ramadan Al-Azhar University Lecture 3
LOGO Lab Supervisor – Dr. WH Lau EE3271 Design Laboratory.
ECE 2211 Microprocessor and Interfacing Chapter 8 The 8088/8086 Microprocessors and their memory and I/O interfaces Br. Athaur Rahman Bin Najeeb Room.
MICROPROCESSORS TWO TYPES OF MODELS ARE USED :  PROGRAMMER’S MODEL :- THIS MODEL SHOWS FEATURES, SUCH AS INTERNAL REGISTERS, ADDRESS,DATA & CONTROL BUSES.
CS-334: Computer Architecture
Chapter 13: I/O Systems Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Chapter 13: I/O Systems I/O Hardware Application I/O Interface.
1 Homework Reading –Review previous material on “interrupts” Machine Projects –MP4 Due today –Starting on MP5 (Due at start of Class 28) Labs –Continue.
04/14/2008CSCI 315 Operating Systems Design1 I/O Systems Notice: The slides for this lecture have been largely based on those accompanying the textbook.
Silberschatz, Galvin and Gagne  Operating System Concepts Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem.
Interrupts What is an interrupt? What does an interrupt do to the “flow of control” Interrupts used to overlap computation & I/O – Examples would be console.
Handheld TFTP Server with USB Andrew Pangborn Michael Nusinov RIT Computer Engineering – CE Design 03/20/2008.
Figure 2.8 Compiler phases Compiling. Figure 2.9 Object module Linking.
I/O Hardware n Incredible variety of I/O devices n Common concepts: – Port – connection point to the computer – Bus (daisy chain or shared direct access)
04/16/2010CSCI 315 Operating Systems Design1 I/O Systems Notice: The slides for this lecture have been largely based on those accompanying an earlier edition.
I/O Systems CS 3100 I/O Hardware1. I/O Hardware Incredible variety of I/O devices Common concepts ◦Port ◦Bus (daisy chain or shared direct access) ◦Controller.
Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.
DMX512 Programmable Theater Lighting Controller Jeff Sand and Kris Kopel Advisor: Dr. Don Schertz May 8, 2001.
Figure 1.1 Interaction between applications and the operating system.
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
Chapter 7 Input/Output. Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats.
Group 7 Jhonathan Briceño Reginal Etienne Christian Kruger Felix Martinez Dane Minott Immer S Rivera Ander Sahonero.
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
NS Training Hardware. System Controller Module.
Serial Peripheral Interface Module MTT M SERIAL PERIPHERAL INTERFACE (SPI)
Input/Output. Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower.
Khaled A. Al-Utaibi  Intel Peripheral Controller Chips  Basic Description of the 8255  Pin Configuration of the 8255  Block Diagram.
SLAAC Hardware Status Brian Schott Provo, UT September 1999.
MICROPROCESSOR INPUT/OUTPUT
Hardware Definitions –Port: Point of connection –Bus: Interface Daisy Chain (A=>B=>…=>X) Shared Direct Device Access –Controller: Device Electronics –Registers:
Interrupts and DMA CSCI The Role of the Operating System in Performing I/O Two main jobs of a computer are: –Processing –Performing I/O manage and.
I/O Systems I/O Hardware Application I/O Interface
1 Lecture 20: I/O n I/O hardware n I/O structure n communication with controllers n device interrupts n device drivers n streams.
ATA Miniport Nuts and Bolts
1-1 Embedded Network Interface (ENI) API Concepts Shared RAM vs. FIFO modes ENI API’s.
Computer Architecture Lecture10: Input/output devices Piotr Bilski.
A Comparative Study of the Linux and Windows Device Driver Architectures with a focus on IEEE1394 (high speed serial bus) drivers Melekam Tsegaye
Timers.
Ethernet Driver Changes for NET+OS V5.1. Design Changes Resides in bsp\devices\ethernet directory. Source code broken into more C files. Native driver.
Chapter 13: I/O Systems Silberschatz, Galvin and Gagne ©2005 Operating System Principles Chapter 13: I/O Systems I/O Hardware Application I/O Interface.
Chapter 13 – I/O Systems (Pgs ). Devices  Two conflicting properties A. Growing uniformity in interfaces (both h/w and s/w): e.g., USB, TWAIN.
Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower than CPU.
Chapter 13: I/O Systems Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Chapter 13: I/O Systems Overview I/O Hardware Application.
بسم الله الرحمن الرحيم MEMORY AND I/O.
Silberschatz, Galvin, and Gagne  Applied Operating System Concepts Module 12: I/O Systems I/O hardwared Application I/O Interface Kernel I/O.
1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.
Chapter 13: I/O Systems.
Software 12/1/2008.
Homework Reading Machine Projects
Module 12: I/O Systems I/O hardware Application I/O Interface
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
CS 286 Computer Organization and Architecture
Homework Reading Machine Projects Labs
Dr. Michael Nasief Lecture 2
CSCI 315 Operating Systems Design
AT91RM9200 Boot strategies This training module describes the boot strategies on the AT91RM9200 including the internal Boot ROM and the U-Boot program.
I/O Systems I/O Hardware Application I/O Interface
Operating System Concepts
13: I/O Systems I/O hardwared Application I/O Interface
CS703 - Advanced Operating Systems
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
Chapter 13: I/O Systems.
Module 12: I/O Systems I/O hardwared Application I/O Interface
Presentation transcript:

WIFI design Guide based PW620-I b/g ----Hardware section Orin.Zhu August 31 st, 2007

PW620-I Block Diagram Front-End Module PA,SW,Balun,Passive BPF(2.45G) 3.1V~4.5V Energy Management Unit (EMU) RF ZIF Section RF Up/Down Converter Baseband Filters High Speed Data Conversion Baseband Processor OFDM/CCK Modulation ARM9 WEP MAC Baseband & MAC SPI I/F BT I/F 3.0V~5.5V1.62V~1.90V40MHz 1.85V EEPROM

System Block i.MX21 PW620-I WIFI b/g SPI1 3.3V TXB V to 3.3V Level translator SPI 1.8V LDO(MIC ) 3.7V to 1.8V 300mA LDO(MIC ) 3.7V to 3.3V 300mA 40MHz, 1.8V,<=20ppm Clock Oscillator

SPI timing Configure—4 wire mode i.MX21 PW620-I MSB first, POL=0, PHA =0, CLK=24MHz, IRQ active high, rising edge triggered IRQ

4-wire SPI mode with IRQ J7I/OActive Pin 2SPI_IRQOHigh Pin 3SPI_CLKI Pin 4SPI_CS#I Pin 5SPI_MISOO Pin 6SPI_MOSII

SPI functions needed by MX21 extern void ssa_spi_reset_drive_low (void); extern void ssa_spi_reset_drive_high (void); extern int ssa_spi_get_irq (void); extern int ssa_spi_init (void); extern unsigned int ssa_spi_read_single8 (void); extern unsigned int ssa_spi_write_single8 (unsigned char value); extern unsigned int ssa_spi_read_single16 (void); extern unsigned int ssa_spi_write_single16 (unsigned short value); extern unsigned int ssa_spi_read_multi (unsigned char *dst, unsigned int count); extern unsigned int ssa_spi_write_multi (unsigned char *src, unsigned int count); For more details info about how to porting in Mx21, contact me.

PCB Outline view Cell Area Multi Area for PCB & SMT Note: For connection among boards, use the stamp holes(2mm length) For panel, use four mark & mount holes.

PCB parameters requirements Stack layer: TOP  VCC  GND  BOTTOM Board impendance: 60ohm +/- 5% Thinkness: 2mm Material: FR-4

Software Section

SPI registers in CX53121 #define SPI_ADRS_ARM_INTERRUPTS 0x00 #define SPI_ADRS_ARM_INT_EN 0x04 #define SPI_ADRS_HOST_INTERRUPTS 0x08 #define SPI_ADRS_HOST_INT_EN 0x0c #define SPI_ADRS_HOST_INT_ACK 0x10 #define SPI_ADRS_GEN_PURP_1 0x14 #define SPI_ADRS_GEN_PURP_2 0x18 #define SPI_ADRS_DEV_CTRL_STAT 0x26 // high word #define SPI_ADRS_DMA_DATA 0x28 #define SPI_ADRS_DMA_WRITE_CTRL 0x2c #define SPI_ADRS_DMA_WRITE_LEN 0x2e #define SPI_ADRS_DMA_WRITE_BASE 0x30 #define SPI_ADRS_DMA_READ_CTRL 0x34 #define SPI_ADRS_DMA_READ_LEN 0x36 #define SPI_ADRS_DMA_READ_BASE 0x38 #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000 #define SPI_CTRL_STAT_START_HALTED 0x4000 #define SPI_CTRL_STAT_RAM_BOOT 0x2000 #define SPI_CTRL_STAT_HOST_RESET 0x1000 #define SPI_CTRL_STAT_HOST_CPU_EN 0x0800 #define SPI_DMA_WRITE_CTRL_ENABLE 0x0001 #define SPI_DMA_READ_CTRL_ENABLE 0x0001

SPI registers in CX53121 #define FIRMWARE_FILE "/etc/isl3825.arm" #define FIRMWARE_ADDRESS 0x20000 #define PDA_FILE "/etc/pda.bin" #define SPI_MAX_PDA_SIZE 2560 #define SPI_TIMEOUT 100 /* msec */ #define SPI_MAX_RX_PACKETS 32 #define SPI_MAX_TX_PACKETS 32 #define SPI_MAX_PACKET_SIZE 3600 #define SPI_TARGET_INT_WAKEUP 0x #define SPI_TARGET_INT_SLEEP 0x #define SPI_TARGET_INT_RDDONE 0x #define SPI_TARGET_INT_CTS 0x // clear to send #define SPI_HOST_INT_READY 0x #define SPI_HOST_INT_UPDATE 0x #define SPI_HOST_INT_SW_UPDATE 0x #define SPI_HOST_INT_WR_READY 0x #define SPI_HOST_INT_CTS 0x // clear to send #define SPI_HOST_INT_DR 0x // data ready

Software View of Application PW620 * During boot process, WLAN firmware is downloaded to target as a package. * The driver provides a Network Interface as well as a Control Interface to the Application Software and Host Operating System (OS)

Software system View SPI1/SDIO interface PW620 Module SPI1/SDIO interface Interface APIMessage API SPI1/SDIO interface

Function API Initialize the HHAL and the initial configuration of the target module Start /stop/reset the target via command Send request/data message to the target During reset, bootloads the firmware to the target and re-initializing Register the callback routine for DMA events, management event, transmit/receive events Hookup function Memory dump function Boot-up processing

Power up Boot-ROM code initializes the internal DMA channel Target write its mailbox to generate one interrupt request Asking the host to send firmware Host detects the IRQ, and it DMAs A small boot agent to target Once completion, host will write one scratch register to inform the target Host configures the SPI clock, Polarity & phase by writing scratch register The target responses it, then execute the boot agent Host writes the start command to target….

Platform API Initialize the platform layer before/after boot-up Read/write the HW registers and interrupt status Enable/disable the MAC function DMA transfer between host and target

Driver Block WLAN driver stack BUS driver stack Target– PW620

WLAN driver stack –Host side Client driver HHAL Platform Layer HOSAL WLAN Driver Stack Forward incoming request to platform layer, Initialize, configure, send and receive the data to/from the target using SPI read/write function Client application

Platform layer – Host side This layer performs information exchange between host & target via SPI mailbox & scratch registers, SPI_DMA, internally, also the external interrupt output. It follows a certain protocol and is implemented in this layer Power up Download firmware To PW620 SPI Start PW620 module via customer command 3825lmac.h The actual WLAN specific communication between the Host and the Target is performed through management and data request and confirm messages. DMA

HOSAL layer --- Host side OS & related structure initialize Memory management Timer Queue Interrupt Thread Event Lock

Bus driver stack –Host side SPI Client Bus driver Host controller driver HOST OS Enumeration, initialize, Configuration via client driver Common (layer) SPI driver for target & client driver Send & receive commands to the target, also, pass the interrupt To bus driver & spi client layer Host driver ioctl

Linux System software architecture Driver Softmac DDK SPI_BSPUMACLMAC Implement Linux WIFI driver for conexant chipset \driver\Core\ \driver\SPI\ (Bus drvier) SPI low- level driver WIFI protocol Independent of OS/Bus ISL3825.arm Firmware Little-endian

SoftMAC DDK Applications Driver Include Lib Patches Makefile Config Run.sh

Context

How to upload firmware to CX Read LMAC firmware from NOR flash/hard-disk, from FIRMWARE_ADDRESS Note: the firmware is read as file system. 2.Reset the cx53121 by writing to reset register of WIFI via SPI interface 3. Read data from firmware file into buffer kmalloced by OS. 4. find LMAC description (first block must contain LMAC descriptor) by UMAC and transfer the return value to the driver. 5. Compare the version info of LMAC and UMAC 6. Write CMD & data from buffer into CX53121 via SPI write function 7. Enable the CX53121, the firmware will start! 8. LMAC firmware initializes and generates one Device Initialized interrupt to OS, and wait for OS processing. 9. Interrupt handler triggers the init procedure of the UMAC & driver.