CRU Weekly Meeting Erno DAVID, Tivadar KISS Wigner Research Center for Physics (HU) 18 November, 2015

2 News TPC turbulences Maybe the bandwith of the GBT links are not enough – new read-out options is investigated Maybe the CRU buffer size is not enough – CRU for TPC can be questioned The TPC team promises some answers to these question by next week Let us be patient and cooperative Let us continue our work 2nd CRU Firmware Development Workshop at CERN proposed dates: Jan by that time all the Indian colleagues will arrive at CERN (Tapan said) topics to be defined and sand out a call

3 Central Git Server Service GitHub vs. CERN GitLab: O2 Plenary Meeting, Tuesday, 10 November 2015, CWG 11: Software Repository - Dario Berzano ( The proposal: GitHub for open source software CERN GitLab for software (and firmware) with restrictions (e.g. fw with licensed vendor IPs) CRU CERN GitLab repository: Currently alice-cru and alice-tpc-cru added as developers. Please check your GitLab account if you plan to contribute.

4 Quartus flow Central Git repository Local Git repository Local working directory for Quartus project Quartus II 64-Bit Version Build 153 Tested under Windows (7, 8.1) and Linux (Ubuntu 14.04) /core/firmware/src – contains firmware source codes /core/firmware/scripts – contain the Quartus TCL build scripts (project creation, I/O settings, source codes) /tcp/firmware/src and /tcp/firmware/sripts – TPC specific source codes and scripts quartus_sh --script %CRU_GITDIR%/tpc/firmware/scripts/build.tcl ; Flow Elapsed Time ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time ; ; Analysis & Synthesis ; 00:11:00 ; 2.1 ; 5483 MB ; 00:12:39 ; ; Fitter ; 00:34:58 ; 4.9 ; MB ; 02:25:57 ; ; Assembler ; 00:01:47 ; 1.0 ; 7626 MB ; 00:01:46 ; ; Timing Analyzer ; 00:05:09 ; 7.4 ; MB ; 00:24:53 ; ; Total ; 00:52:54 ; -- ; -- ; 03:05:15 ;

5 Modelsim flow Central Git repository Local Git repository Local working directory for Modelsim ModelSim ALTERA STARTER EDITION 10.3d (VHDL only, no mixed mode) /core/firmware/sim – contains the basic simulation framework (TTS, GBT, PCIe, DCS pattern gen/chk) /tpc/firmware/sim and /tpc/firmware/scripts –detector specific user logic, testbenches and scripts The main idea: Provide a functional test ability before the synthesis Provide the detector specific user logic with some inputs (TTS, GBT, DCS) Accept the output from user logic and check it (PCIe)

6 Git flow Folder based permissions: LHCb’s soulution It requires Gitolite features for folder permission (git push control) It is not supported by GitLab Protected Git branches: Supported by GitLab (the master branch protected by default) Possible flow: separated branches for core and tpc development, and merge into master periodically Fork / Pull request model: The proposed flow by O2 team Fork the central repository, implement features, send a pull request to central team

10G PON 2014 (11.2 Gbps)

10G PON 2015 (9.6 Gbps)

GBTX LTU CRU HHHHHH K28.5 LHC Clock Distribution PON TX clock (240 MHz) LHC clock (40 MHz) 9.6 PON Downlink 4.8 GBT Downlink... PON RX clock (240 MHz) Reconstructed LHC clock (40 MHz) GBT TX clock (120 MHz) 40 bit Reconstructed LHC clock (40 MHz) GBT REF clock (120 MHz) PON Frame 6x40 40 MHz GBT Frame 3x40 40 MHz GBT Transmitter PON Receiver

CRU Arria 10 FPGA 10 GBT Bank Clocking Scheme 10G PON Transceiver 10G PON REFCLK External PLL + Jitter Cleaner GBT Transmitters Bank 0 GBT Receivers Bank 0 TTS_RX_CLK 240 MHz GBT_BANK_0_REFCLK 120 MHz 120MHz GBT Gear Box 40MHz 80 bit TTS 240MHz 40MHz 184 bit Downlink Logic Bank 0 IOPLL 40 bit 120MHz40MHz IOPLL 80 bit 40 bit Uplink Logic Bank 0 RX SCA RX GBTx 2 bit TX SCA TX GBTx 2 bit 250MHz 256 bit GBT Bank 0 – Link (Consist 6 adjacent bonded Arria 10 transceiver) 250MHz 256 bit The number of GBT Banks is equal to GBT Links /

11 LHC Clock Distribution Uncertainty Point 1: The 40 MHz LHC clock must be reconstructed based on the K28.5 symbol position K28.5 position precision, 1/9.6 GHz => ps How to adjust and measure the 40 MHz PLL phase? Point 2: The phase uncertainty originated from external jitter cleaner and PLL Based on the PON teams report this can be controlled Point 3: The Arria 10 transceiver first produce the 2400 MHz serial clock from the external 120 MHz reference clock then it divides back to produce the 120 MHz TX clock Is it controllable the phase difference between the 120 MHz ref. clk and TX clk?

Arria 10 Transmitter Clocking

Arria 10 Receiver Clocking