Thomas J. Watson Research Center © 2006 IBM Corporation Statistical Timing in a Practical 65 nm Robust Design Flow Chandu Visweswariah

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 2 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop The power of statistical formulas

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 3 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Acknowledgements  The extended statistical timing, statistical optimization, timing support and timing methodology teams at IBM Yorktown, Fishkill, Burlington, Poughkeepsie, Rochester and Waltham Caveat  This presentation is mostly ASIC-focused, although microprocessor design issues will be mentioned (time permitting)

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 4 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Outline  Yield loss mechanisms and the tradeoffs involved  What is robust design?  A timing closure methodology based on statistical timing  Myths about statistical timing  Interesting challenges –early/late splits and CPPR –at-speed test –metrics for optimization –delay modeling for 45 nm –hierarchical statistical timing

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 5 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Catastrophic vs. parametric yield loss Dummy fill Source: NEC 0% 20% 40% 60% 80% 100% 350nm250nm180nm130nm90nm Yield Parametric (design-based) Lithography Based Defect Based

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 6 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Increasing and inevitable parametric variability *D. J. Frank et al, Symp. VLSI Tech., 1999 Litho-induced variability Random dopant effects * Oxide thickness Interconnect CMP and RIE effects

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 7 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Normalized metal resistance data over 3 months  Wafer means change over time  Values are “out-of-spec,” need to yield within WAC limit We would like to retain these wafers

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 8 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Manufacturing for predictable performance  Cp and Cpk (Process Capability Indices) measure manufacturing predictability  Manufacturing typically (but not always) outperforms spec. limits Lower spec. limit Upper spec. limit Nominal spec.

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 9 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Normalized cumulative statistics  Distributions are not Gaussian (but usually close)

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 10 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Ring oscillator performance distribution spec Slower Percentage of chips  Color coding is by wafer  Hardware is faster/tighter than predictions

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 11 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Normalized metal resistance across manufacturing lines  Designs must yield at multiple fabs.

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 12 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Normalized single-level capacitance distribution  Variability is enormous!

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 13 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Any performance left in worst-case design? 90 nm 65 nm 45 nm

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 14 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop What do we do with all this variability? As we know, There are known knowns. There are things we know we know. We also know There are known unknowns. That is to say We know there are some things We do not know. But there are also unknown unknowns, The ones we don't know We don't know. Donald H. Rumsfeld 1 1 Dept. of Defense news briefing, 2/12/02, linebreaks mine Known knowns Known unknowns Unknown unknowns Statistical timing and power analysis

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 15 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Robust circuit design  Its the sensitivities, stupid! First order model

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 16 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Delay modeling Fast chip vs. slow chip Chip means Can get across- parameter RSS relief Systematic ACV Can get space- dependent relief Random ACV Can get down-a- path RSS relief EarlyLateEarlyLate

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 17 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Model-to-hardware correlation Mean RO delay RO delay Fast chip Slow chip Late Early

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 18 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Bounding distributions  Bounding distributions provide protection from various sins!

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 19 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Statistical-timing-based flow  Conduct statistical timing with correlations –predict timing slacks in “canonical” form parameterized by the sources of variation  “Project” flop slacks to worst corner; if positive, we are safe  Get “debits” and “credits” –mixed-mode projection –spatial –coupling noise –independently random  Check sensitivities –alternative statement of Murphy’s law: “Variability exacerbates poor design!” –encourage “balanced” or “robust” design  Check single-corner timing with all bells and whistles  Optimization and fix-up –use incremental statistical timing –various diagnostics available

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 20 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Myths about statistical timing  “The main reason for statistical timing is within- die variations” … “Variability is dominated by within-die variations” … “The main frequency limiter is within-die variations”  Random dopants are the only truly statistical phenomena  “Statistical timing is a good idea so long as you don't assume that variations are statistical,” said TI's (Dennis) Buss. About the only thing that's truly statistical, he said, are random dopant fluctuations.” (From EE Times article 7/26/06 by Richard Goering)

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 21 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Courtesy Anne Gattiker, IBM

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 22 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Courtesy Anne Gattiker, IBM Across-wafer variations

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 23 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Interesting challenges: early/late splits and CPPR LL 1 LL 2 CL LL 3 late data Same buffer has different delays on early/late paths early clock Undue pessimism

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 24 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Interesting challenges: at-speed testing Chip Under Test PLL Clock control Logic RefClk StartTest Clk From tester: Scan & Test Clocks Test Data [Courtesy Gary Grise] Clk Scan Clock PLL Output Last Scan-Load CycleAt-Speed TestScan Unload Cycles

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 25 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Interesting challenges: at-speed testing  Each point in the process space can have a unique critical path  How to come up with a set of test vectors that tests for parametric variations in all parts of the process space?  How to measure coverage thereof?  How to test against workload-related defects?  How to test against fatigue-related defects? Critical

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 26 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Interesting challenges: metrics for optimization  Slack is lacking –different critical paths in different parts of the process space –slack is a distribution –slack does not give robustness information –relative ordering of paths slack does not give correlation information Other open problems  Delay+power+noise variational modeling for 45 nm  Robust optimization, fix-up  Hierarchical robust design

Thomas J. Watson Research Center © 2006 IBM Corporation, do not copy without permission 27 of 27Statistical Timing in a Practical 65 nm Robust Design FlowC2S2 Workshop Conclusions  Must protect against parametric variability –high dimensionality, hence the need for statistical timing –hence the need for robust design –hence the need to check sensitivities –hence the need for statistical timing!  IBM has adopted a statistical-timing-based robust design flow for 65 nm ASICs  Many open and interesting challenges remain