© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust © 2008 Pearson Education Finite state machines

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed In this lecture we cover: Introduction to Finite State Machines (FSMs) Mod-4 Counter example

Finite State Machines vs. Combinational Logic Units  Combinational logic units are a type of logic circuit whose output is a pure function of the present input only.  Finite State Machines, used in sequential logic, have outputs that depend on both the present input as well as the history of the input.

A Finite State Machine  A sequential logic unit which  Takes an input and a current state  Produces an output and a new state  It is called a Finite State Machine because it can have, at most, a finite number of states.  It is composed of a combinational logic unit and flip-flops placed in such a way as to maintain state information.

Finite state machine block diagram  State memory: Set of n flip-flops that hold the state of the machine (up to 2^n distinct states)  Next state logic: Combinational circuit that determines the next state as a function of the current state and the input  Output logic: Combinational circuit that determines the output as a function of the current state and the input

Finite State Machine types  Mealy machine: The output depends on the current state and input  Moore machine: The output depends only on the current state  State = output state machine: A Moore type FSM where the current state is the output

Representing a Finite State Machine  It can be represented using a state transition table which shows the current state, input, any outputs, and the next state. Input Current State Input 0 Input 1 …. Input n State 0 State 1 …. State n Next State / Output …. Next State / Output …. …. ….

Representing a Finite State Machine  It can also be represented using a state diagram which has the same information as the state transition diagram. State 0 State 1 Input / Output

Example 1: A Modulo-4 Synchronous Counter  Counts from 0 to 3 and then repeats.  It has a clock input (CLK) and a RESET input.  Outputs appear as a sequence of values (q 1 and q 0 ) at time steps corresponding to the clock.  As the outputs are generated, a new state (s 1 s 0 ) is generated which takes on values of 00, 01, 10, and 11 and are fed back to the input.

The Mod-4 Counter Requires four states, encoded in binary, with at least two bits for them to be encoded uniquely. ▫ A = 00 ▫ B = 01 ▫ C = 10 ▫ D = 11 The input requires only a single bit. ▫ 0 | 1

State Transition Diagram for the Mod-4 Counter

State Table for the Mod-4 Counter

State Assignment for the Mod-4 Counter

Truth Table for the Mod-4 Counter

Logic Design for Mod-4 Counter

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Next lecture covers: Advanced FSM examples: Sequence detector example Vending machine example