Forward Trigger Upgrade and AuAu Pattern Recognition V. Cianciolo, D. Silvermyr Forward Upgrade Meeting August 18-19, 2004

2 Motivation This group is proposing to upgrade the Muon Arms to increase their trigger rejection power in pp collisions. We suffer from significant inefficiencies in central AuAu events. Can we solve both problems at once?

3 AuAu Efficiency Loss J/  efficiency in central AuAu events is ~20 (30)% for the North (South) Arm Reconstruction code still under development, but ~50% of clusters have contributions from >1 track. The statistical improvement cannot be much better than x3. –For most measurements it is hard to justify large expenditures for a “marginal” improvement. –For low-statistics, low S/N signals (J/  in central AuAu collisions) this improvement can be crucial (e.g., by reducing a 3-year measurement to a 1-year measurement). Also a systematic effect. –When the efficiency is low any error on our calculation of that efficiency (due to incomplete simulation of real- life effects) is magnified in the cross section determination. North Arm J/  Efficiency

4 How Can The Trigger Upgrade Help? Reduce Occupancy Assume 1-degree  -slices (based on discussions w/ Wei) We set a goal of 0.5% occupancy and find we need 28 (20)  -pads per  - slice for station 1 (station 3). Plots show occupancy (vs.  ) South Arm MuTR Stations 1 and 3 for 200 AuAu “central” events. –Minimum bias events scaled up by x4. –24 equal-  pads per  -slice. –Note: for station-1 equal-  pads are probably not the optimum choice, but that’s not important for now.  (degrees) Occupancy

5 Would 2D info really help with AuAu reconstruction? We can’t make a iron-clad case now. –Someone would need to incorporate a hypothetical detector into PISA, run some simulations and re- tool the reconstruction algorithm. –Hugo, Melynda, etc. could comment on the feasibility of this. However, consider all hits on station-3 in MB AuAu events. We determine the number of possible partner hits on station-1 based on two cuts: –  (  ) < /15(  ) –  (  ) < /15(  ) &&  < 1 –These two cuts are appropriate for 2.5 GeV muons (p min of interest to heavy flavor) We then count the number of combinations per station-3 hit (left) and per event (right). The basic contention motivating these plots is that high-strip occupancy leads to stereoscopic ambiguity, thus eliminating much of the segmentation in the orthogonal direction at the pattern recognition stage.  (degrees) Red –  -cut only Black –  and  -cuts Red –  -cut only Black –  and  -cuts # Combinations per St3 Hit # Combinations per Event

6 “Known” Benefits of 2D Info You really know where the hits are. –You know how many hits contributed to a cluster. –This must help w/ fitting cluster position. –Deprecate the weight of those clusters? Most hits have no potential high-momentum partner – why do any cluster fitting for them? You have (many) fewer combinations that need to undergo detailed reconstruction. Both seem like great potential for significantly reducing execution time.

7 Downstream Chamber Location? Collision-related hit density highest in “gap-5” due to splash off DX. Tight  correlation should be lost in “gap-5” due to multiple scattering.  For the trigger, go in between station-3 and gap-0. Having 2D info in back of the MUID may help with heavy flavor measurements in AuAu and may also be important for W physics, but not from a trigger point of view. They would make it significantly more difficult to falsely extend a track by combining it with a hit from behind. Gap 0 Gap 1 Gap 2 Gap 3 Gap 4 “Gap 5” MuID Gap Hits (200 AuAu MB Events)

8 PC FEE David points out that there are 90k channels of PC electronics currently on the shelf (~half in the form of chips, half assembled into Readout Cards (ROCs)). Each ROC has 48 channels and 4 trigger bits. –With suggested segmentation a ROC would cover a 2 degree slice, and each 1 degree slice would have 2 trigger bits (one for low- , one for high-  ). Each FEM reads out 45 ROCs, or 90 degrees. –Need 4 FEMs/chamber; 8 per arm.

9 Connecting it to MUIDLL1 PC not a part of the trigger, but 4 bits per ROC are available. From previous slide we have 45*4=180 bits per FEM. This fits on two 6XBCLK fibers. –Need a New Trigger Board (one per FEM) but the pieces are all literally copies of what is on a MUID ROC. An entire arm (16 fibers) would fit onto one Generic LL1 Board PC FEM 8/arm New Trigger Board 8/arm 6XBCLK Generation MuMUX6 FPGA G-Link Daughterboard BCLK Data (1) 45*2 bits MuMUX6 FPGA G-Link Daughterboard Data (2) 45*2 bits Generic LL1 Board Accepts all fibers for one arm

10 Timing? Up to now this talk has had no mention of using timing info. If it is really needed I don’t think the PC FEE option works. One possibility may be to use MUID FEE with a modified ROC. The signals would go through some (new) appropriate preamp and discriminator. They would be gated on a signal derived from BCLK with width and delay programmed to gate in only collision-related signals. The simplest solution would be to use 96 channels/ROC. Then all the rest of the system could be used unchanged. 48 Channels per PC DMU BCLK w/ programmable width, delay Signal i Signal i+1 Signal i+2 Signal i+3 Signal i+4 Data FIFO BCLK w/ programmable width, delay Signal i Signal i+1 Signal i+2 Signal i+3 Signal i+4 BCLK w/ programmable width, delay Signal i Signal i+1 Signal i+2 Signal i+3 Signal i+4 BCLK w/ programmable width, delay Signal i Signal i+1 Signal i+2 Signal i+3 Signal i+4

11 Modified MUID FEE The solution on the previous slide represents 9 FEMs/arm, which is probably somewhat expensive, and is overkill for two reasons: –Bandwidth limits (conversion time and DCM communicaiton) allow us to have many more signals/ROC. –We don’t need to send all the accepted event bits to the trigger – only 1/12 with the suggested numerology. Various limitations suggest a maximum of 288 channels/ROC. –This would reduce the requirements to 2 FEMs/arm. Necessary development for this option: –A scheme to get all those signals onto a ROC. New transition cards and passthrough backplane. –A plan for processing all those signals on a ROC. Board real estate may be a problem, but reduced complexity (no CFD, no complicated timing adjustment circuitry) may solve this. –A trigger interface board, as described for PC FEE option. It could live in the MUID FEM crate. –Relatively minor mods to the FEM firmware.