Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design.

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Presentation transcript:

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design

Lecture #8 Page 2 VHDL Operators VHDL Operators - Data types define both "values" and "operators" - There are "Pre-Determined" data types Pre-determined = Built-In = STANDARD Package - We can add additional types/operators by including other Packages - We'll first start with the STANDARD Package that comes with VHDL

Lecture #8 Page 3 VHDL Operators Logical Operators - works on types BIT, BIT_VECTOR, BOOLEAN - vectors must be same length - the result is always the same type as the input not and nand or nor xor xnor

Lecture #8 Page 4 VHDL Operators Numerical Operators - works on types INTEGER, REAL - the types of the input operands must be the same +"addition" - "subtraction" * "multiplication" / "division" mod "modulus" rem "remainder" abs "absolute value" ** "exponential" ex) Can we make an adder circuit yet? A,B: inBIT_VECTOR (7 downto 0) Z : out BIT_VECTOR (7 downto 0) Z <= A + B;

Lecture #8 Page 5 VHDL Operators Relational Operators - used to compare objects - objects must be of same type - Output is always BOOLEAN (TRUE, FALSE) - works on types: BOOLEAN, BIT, BIT_VECTOR, CHARACTER, INTEGER, REAL, TIME, STRING ="equal" /= "not equal" "greater than" >= "greater than or equal"

Lecture #8 Page 6 VHDL Operators Shift Operators - works on one-dimensional arrays - works on arrays that contain types BIT, BOOLEAN - the operator requires 1) An Operand (what is to be shifted) 2) Number of Shifts (specified as an INTEGER) - a negative Number of Shifts (i.e., "-") is valid and reverses the direction of the shift sll"shift left logical" srl "shift right logical" sla "shift left arithmetic" sra "shift right arithmetic" rol "rotate left" ror "rotate right"

Lecture #8 Page 7 VHDL Operators Concatenation Operator - combines objects of same type into an array - the order is preserved & "concatenate" ex) New_Bus <= ( Bus1(7:4) & Bus2(3:0) )

Lecture #8 Page 8 VHDL Operators STD_LOGIC_1164 Operators - To expand the data types we have in VHDL, we include the IEEE Package "STD_LOGIC_1164" - This gives us the data types: STD_LOGIC STD_LOGIC_VECTOR - This gives us all of the necessary operators for these types Logical Numerical Relational Shift

Lecture #8 Page 9 VHDL Operators Assignment Operators - The assignment operator is <= - The Results is always on the Left, Operands on the Right - Types need to all be of the same type - need to watch the length of arrays! Ex)x <=y; a <= b or c; sum <= x + y; NewBus <= m & k;

Lecture #8 Page 10 Delayed Assignments Delay Modeling - VHDL allows us to include timing information into assignment statements - this gives us the ability to model real world gate delay - we use the keyword "after" in our assignment followed by a time operand. Ex) B <= not A after 2ns; - VHDL has two types of timing models that allow more accurate representation of real gates 1) Inertial Delay (default) 2) Transport Delay

Lecture #8 Page 11 Delayed Assignments Inertial Delay - if the input has two edge transitions in less time than the inertial delay, the pulse is ignored said another way… - if the input pulse width is smaller than the delay, it is ignored - this models the behavior of trying to charge up the gate capacitance of a MOSFET ex) B <= A after 5ns; any pulses less than 5ns in width are ignored.

Lecture #8 Page 12 Delayed Assignments Transport Delay - transport delay will always pass the pulse, no matter how small it is. - this models the behavior of transmission lines - we have to explicitly call out this type of delay using the "transport" keyword ex) B <= transport A after 5ns; B <= transport not A after t_delay; -- here we used a constant