Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects Fei Wang 1,2, Yu Hu 1, Huawei Li 1, Xiaowei Li 1, Jing Ye 1,2 1 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences 2 Graduate University of Chinese Academy of Sciences Yu Huang 3 3 Mentor Graphics Corporation International Test Conference Santa Clara, CA, Oct 26-Oct 31, 2008

Purpose Object –Faulty circuit contains compound defects Problem –How to diagnose scan chains when existing compound defects? –How to guarantee diagnostic accuracy, resolution and efficiency? Method –Deterministically generate diagnostic patterns under certain constraints –Statistically failure analysis to locate the faulty scan cell scan chain defects and system logic defects co-exist on the chip

Outline Background –Motivation –Related work –Our contributions Proposed method –DDPG algorithm –Compound defect diagnosis process Experimental results

Motivation Why compound defect diagnosis –Both scan chains and system logic occupy significant area Scan chains associated area: 30% [Kundu VTS’93] Scan chain failures: 50% [Yang ICCD’05] –Assume system logic is fault-free will lead to misdiagnosis

Related Work Scan chain diagnosis Hardware based solutionsSoftware based solutions Partner scan chain Partner scan chain Insert XOR gates Insert XOR gates [Schafer VTS’92] [Narayanan ITC’97] Custom scan cell Custom scan cell [Edirisooriya VTS’95] Simulation based Simulation based DDPG [Huang ITC’07] [ Tzeng TCAS’07 ] Production test patterns Production test patterns Functional patterns Functional patterns [Guo ITC’07] [Li TVLSI’05] Capture state Capture state Propagate state Propagate state

Related Work Scan chain diagnosisHardware based solutions Partner scan chain Partner scan chain Software based solutions Custom scan cell Custom scan cell Simulation based Simulation based DDPG  High area and routing overhead  Unconventional DFT flow  Unguaranteed resolution  Unguaranteed accuracy  Impractical assumption: system logic is fault free ！ Insert XOR gates Insert XOR gates

Our Contributions Features –First DDPG for compound defects –Effectively diagnose scan chains with dozens of system defects Approach –Propagate the state of the targeted scan cell to multiple observation points –Statistical failure analysis to locate the faulty scan cell Key results –Accurately diagnose faulty cell with dozens of system defects –Tolerate system logic faults without degradation of chain diagnostic resolution

Outline Background –Motivation –Related work –Our contributions Proposed method –DDPG algorithm –Compound defect diagnosis process Experimental results

7 Fault Model SI Downstream Upstream SO Fault ModelExpected UnloadingActual Unloading SA SA STR STF FTR FTF

Basic Idea of DDPG SI SO G1 G4 G SI SO G3 G5 g e a b c f O3O3 O3O3 PI 1 =0 PI 2 =1 i x x 0/0 x 1/0 0/0 x x x 1/1 1/0 x x 1/1 x x x x 1/0 x x x x 1/1 0 x x x x x x 0 x x x 1 x x Targeted cell Vulnerable-PPI Protection-PPI Trigger-PPI Vulnerable-PPO Protection-PPO Actual STR System defect

DDPG Algorithm Overview Select cell i from Suspect_Cell_Set, build Output_Set i Generate a pattern to propagate cell i state to n reliable observation points (ROP) within Output_Set i Success? Output_Set i ∈ Ø ? Suspect_Cell_Set ∈ Ø ? Save the pattern, delete the n ROPs from Output_Set i Y Delete the targeted cell i from Suspect_Cell_Set Y N N End Y N n>1 ? n=n-1 N Y

DDPG Constraints-Loaded Value Constraints on loaded values –Not constrain all scan cells on the faulty chain only constrain the cells that sensitize fault propagation paths –The constrained scan cells can be anywhere on the faulty scan chain Guarantee the patterns can be loaded correctly –The targeted scan cell can be sensitized and its state can be propagated to ROPs

DDPG Constraints-Captured Value Constraints on captured values –The state of ROPs can be safely unloaded –For stuck-at faults, ROPs could be downstream cells of LB in the faulty scan chain good scan chains POs –For timing faults, ROPs could be all cells except the targeted cell in the faulty scan chain good scan chains POs

DDPG Constraints-Sensitization Sensitize Fault Propagation Path –off-path inputs of all the gates on propagation path are constrained to non-controlling values –Specify the minimum number of ROPs (n≥2) Pick 3 observation points Pick at least one observations points SA0 j j j Pick 2 from 3

Apply Constraints to Netlist G4 G G5 b c f PI 1 i h P1 P1P2 P2 SI SA0 j (b, f, h) (b, f, i) Constraint Circuit Sensitized path number ≥ 2 ？ STR

Compound Defect Diagnosis Process Calculate a weight w(pat Ci,j ) for each pattern pat Ci,j w(pat Ci,j )= # of ROPs Ci,j / # of total ROPs Calculate a load error probability LEP(C i, j ) for each scan cell C i LEP(C i, j )=H Ci,j / # of ROPs Ci,j Calculate the suspect score pat C16,1 pat C16,2 pat C16,3 C0C0 C4C4 C 16 C 21 C8C8 O3O3 pat C16,1 =3/10 pat C16,2 =4/10 pat C16,3 =3/10 LEP(C 16,1 )=1/3 LEP(C 16,2 )=4/4 LEP(C 16,3 )=2/3 WLEP(C 16 )=7/10

Outline Background –Motivation –Related work –Our contributions Proposed method –DDPG algorithm –Compound defect diagnosis process Experimental results

Experimental Setup Five ISCAS ’ 89 benchmark circuits Key parameters –Each circuit has two scan chains –n=2, max(|Output_Set i |)=20 Experimental steps For (cell=0;cell<L; cell++) { Inject a timing fault to cell Run DDPG and simulation, calculate Hit_Rate While (! misdiagnosis) { Randomly inject a SA1/SA0 fault to system logic Run DDPG and simulation, calculate Hit_Rate }

Experimental Results CUTSA0SA1FTFFTRSTFSTR Hit_RateABABABABABAB s s s s s Table 1. Hit_Rate of the proposed DDPG method A: system logic is fault-free B: one SA fault in system logic

Robustness Evaluation: s38584 (a) No system logic faults(b) 20 system logic faults (c) 40 system logic faults(d) 68 system logic faults

Robustness Evaluation: All CUTs CUT # of SA0 faults # of SA1 faults # of FTF faults # of FTR faults # of STF faults # of STR faults s s s s s Table 2. The number of faults injected into CUT when misdiagnosis happens

Diagnostic Resolutions CUT MethodSA0SA1FTFFTRSTFSTR s9234 DDPG 2.21/61.75/51.19/21.16/31.22/31.21/4 Li /335.7/145.5/134.8/143.3/86.9/19 s15850 DDPG 2.23/62.30/81.04/21.03/21.02/21.07/2 Li /72.1/72.7/72.1/72.0/72.1/7 s38584 DDPG 2.93/101.73/81.02/31.03/21.02/31.03/2 Li /124.6/153.6/125.6/133.8/123.4/10 Table 3. Diagnostic resolution (Average/Worst)

DDPG Time CUTSA0SA1FTFFTRSTFSTRAvg. s s s s s Table 4. Average pattern generation time (second) for a scan cell

Conclusions First DDPG for compound defects Statistical failure analysis for compound defects Tolerate dozens of faults in system logic without degradation of chain diagnostic resolution

Thank you! Questions?