Lecture 2: Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

2 Overview Last Lecture’s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter MIPS Arithmetic Instructions Register File and Register Naming Convention

3 Review Intro to Computer Architecture Course Style, Philosophy and Structure High Level, Assembly, Machine Language Anatomy of computer system

4 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction

5 Stored Program Computer

6 Stored Program Computer (object code in memory)

7 The process of executing instructions Instruction Fetch PC has the address of the next instruction to be fetched so the control unit fetches the instruction whose address is in PC, and puts it into IR.

8 Next Cycle: ? Control unit decodes the instruction and fetches the operands

9 Execute Data path executes the instruction as directed by the Control unit

10 Instruction formats in R3000 Instruction Categories –Load/Store –Computational –Jump and Branch –Floating Point coprocessor –Memory Management –Special R0 - R31 PC HI LO OP rs rt rdsafunct rs rt immediate jump target 3 Instruction Formats: all 32 bits wide Registers R-format I-format J-format

11 Executes (Reg – Reg) Data path executes the instruction as directed by the Control unit

12 Mem (Reg – Reg) No operation takes place in this cycle

13 WB (Reg – Reg) Result will be put into Reg #2

14 Question What if the CPU executes a load instruction lw $2,504($1) what happens in Exe, Mem, and WB

15 RISC: Reduced Instruction Set Computer RISC philosophy –Fixed instruction length –Load/store instruction set –Limited addressing modes –Limited operations Examples –Alpha processor, Sun SPARC, SGI MIPS, … Design a good instruction set –How well compilers use it; compiler optimization

16 Homework Assignment SPIM a MIPS Interpreter You should have it on the CD; you can also download it off the web, follow the resources page of the course web site. Please read about SPIM and download some programs - you can find a zillion of sample MIPS programs on line – and run them using SPIM.

17 MIPS Arithmetic Instructions Assembly arithmetic statement add $3, $1, $2 sub$3, $1, $2 Each arithmetic instruction performs only one operation Each arithmetic instruction specifies exactly three operands Destination  source1 op source2 The operands should be the contents of the datapath’s register files The operand’s order is fix: Destination first

18 An example If b is in register $1, c in $2, d in $3, and the result supposed to be in $4 h = (b – c) + d sub$5, $1, $2 add$4, $5, $3

19 MIPS Register file Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file –Holds thirty-two 32-bit registers 2 read ports 1 write port Registers are –Faster than main memory –Easier for compiler to use (a * b) – (c * d) – (e * f) any order of these multiplication –Can hold variables so that Code density is improved (fewer bits used to address registers than memory locations)

20 Register file (Cont’d) R#0 R#1 R#2 R#31 32 bits src1 addr src2 addr dest addr Write Back data 32 src1 data 32 src2 data interface

21 Register file (Cont’d)

22 Naming Convention for registers 0zero constant 0 1atreserved for assembler 2v0expression evaluation & 3v1function results 4a0arguments 5a1 6a2 7a3 8t0temporary: caller saves...(callee can clobber) 15t7 16s0callee saves... (caller can clobber) 23s7 24t8 temporary (cont’d) 25t9 26k0reserved for OS kernel 27k1 28gpPointer to global area 29spStack pointer 30fpframe pointer 31raReturn Address (HW)

23 example Compile f = g + h + i if f is in $s0, g in $s1, h in $s2, i in $s3 add $s0,$s1,$s2 add $s0,$s0,$s3 f = (g + h) – (i + j)if f is in $s0, g in $s1, h in $s2, i in $s3, and j in $s4

24 Data transfer instructions Compile G = h - A[7];address of A[0] is in $s1, G in $s2, and h in $s3

25 Example Compile A[20] += A[8];address of A[0] is in $s1

26 Anatomy of data transfer inst. lw $t0, 5($s1) offset Base register Index register (why?)

27 Translate to machine code A[20] +=A[8]; Instructions, so far