HEPMARK2 Consiglio di Sezione 9 Luglio 2012 Michele Michelotto - Padova

Why INFN procurements for Millions of Euro of Worker Node / year –Simulation and Recostruction of HEP events (mainly offline, so High Troughput Computing) How to get the best price/performance How to measure the performance

Benchmark CERN UNIT, VUPS, MIPS, MHz! –We have about GHz of CPU ? Synthetic Benchmark SPEC INT 95 –HLT paper model ( ) SPEC INT 2000 –Computing TDRs ( )

Different usage of SI2K From 2000 to 2006 the default was SPEC CPU INT 2000, (a.k.a. SI2K) used in several ways –Taking data of one cpu from SPEC site –Multiply by the number of cpu in your site –Speed or Rate –Measuring SI2K on real machines with our compiler (gcc) and the default set of optimization switches

CMS sw SIM and Pythia CMS Montecarlo simulation (32bit) and Pythia (64bit) show the same performance once normalized Both Specint 2006 pubblished and Specint 2006 with gcc show the same behaviour SI2K pubblished does not match HEP sw SI2K measured by CERN better but not as good as SI2006

Working group in CERN, INFN, GridKa, Desy, RAL, Univ of Victoria + Esperts from CMS, ATLAS, ALICE, LHCB HEP SPEC 06 –Based not only on INT but also on FP –The same ratio of PF as the job running on lxbatch –Validated against the HEP simulation and reconstruction code

Validation by Working group by WLCG HEP SPEC 06 accepted as reference benchmark in HEP and GRID farm Pledges are now expressed in HS06 T0, T1, T2 measured in HS06

HEP SPEC 06 paper

What we need At least one Worker node for each new family of processor –One from Intel, one from AMD –Always available. Impossibile on make measurements on evaluations machine –Need to rerun on old machines

Milestone 1 SPEC has released in September the version 1.2 of the CPU suite –The score should not change for CPU INT, FP and hence for our HEP SPEC 06 –Need to rerun on all HEPMARK machines

Milestone 2 HEP SPEC 06 at 64 bit Experiments finally moved to full 64bit/64bit HEP SPEC 06 still on 32 bit HEPIX group addressed this issue in the last meeting. We stay with 32 bit since the improvment from 32 to 64 is similar in all processors

New AMD processor 2 x 8 Bulldozer core Each Bulldozer core has 2 int scheduler 32 x-86 core

Many integrated core In contact with G.Maron (LNL) to start exploring the “manycore” processors (MIC) Mainly in the CNAF area of interest:

Backup slides

michele michelotto - INFN Padova bit - HT ON/OFF HT ON:81.81 HT OFF: HT OFF is better up to 11concurrent run

michele michelotto - INFN Padova (2266) vs 2427(2200)

Speed vs Rate

Gcc (gridka) vs SPEC site