1 Chapter 2 Computer Evolution and Performance by Sameer Akram

Key Points Evolution of computers have been characterized by Increasing Processing Speed Decreasing Component Size Increasing Memory Size Increasing I/O Capacity and Speed

Key Points [Increasing Processing Speed] Factors responsible for the great increase in processor speed Shrinking size of micro-processor components; this reduces the distance between components and hence increases speed Organization of micro-processor; pipelining and parallel execution techniques Balancing the performance of various elements, so that gains in one area are not handicapped by a lag in other areas, e.g. processor speed has increased more rapidly than memory access time.

ENIAC - background Electronic Numerical Integrator And Computer John Presper Eckert and John Mauchly University of Pennsylvania Project was a response to U.S. wartime needs during World War II Army Ballistics Research Lab (BRL) was having difficulty in Trajectory tables for weapons Started 1943 Finished 1946 —Too late for war effort Used until 1955

ENIAC - details Decimal (not binary) Memory consisted of 20 accumulators, each capable of holding a 10-digit decimal number Programmed manually by switches Containing more than 18,000 vacuum tubes A ring of 10 vacuum tubes represented each digit Weighing 30 tons Occupying 15,000 square feet 140 kW power consumption during operation Capable of 5,000 additions per second

Stored-Program Concept Task of entering and altering programs for the ENIAC was extremely tedious The programming process could be facilitated if the program could be represented in a form suitable for storing in memory alongside the data Then a computer could get its instructions by reading them from memory and a program could be set or altered by setting the values of portion of memory. This idea is known as Stored-Program Concept.

von Neumann/Turing Von Neumann Princeton Institute for Advanced Studies 1946 –IAS computer Stored Program concept Main memory storing programs and data ALU operating on binary data Control unit interpreting instructions from memory and executing Input and output equipment operated by control unit Completed 1952

Structure of von Neumann machine

IAS - details The memory of IAS consists of 1000 storage locations, called “words” of binary digits (bits) each. Both Data and Instructions are stored in the memory Each number is represented by a sign bit and a 39-bit value A word may also contain two 20-bit instructions, with each instruction consisting of an 8-bit operation code (opcode) and 12-bit address designating one of the words in memory

IAS - details Set of registers Memory Buffer Register Memory Address Register Instruction Register Instruction Buffer Register Program Counter Accumulator Multiplier Quotient

Structure of IAS – detail

IAS - details [Set of registers] Memory Buffer Register: contains a word to be stored in memory, or is used to receive a word from memory. Memory Address Register: specifies the address in memory of the word to be written or read into the MBR. Instruction Register: contains the 8-bit opcode instruction being executed.

IAS - details [Set of registers] Instruction Buffer Register: employed to hold temporarily the right hand instruction from a word in memory. Program Counter: contains the address of next instruction-pair to be fetched from memory. Accumulator and Multiplier Quotient: employed to hold temporarily operands and results of ALU operations.

IAS - details [Instruction Cycle] Instruction Cycle consists of two sub cycles  Fetch Cycle  Execution Cycle

IAS - details [Instruction Cycle]  Fetch Cycle During the Fetch Cycle the opcode of the next instruction is loaded into IR and address portion is loaded into the MAR. This instruction may be taken from the IBR, or it can be obtained from memory by loading a word into the MBR, and then down to the IBR, IR and MAR.

IAS - details [Instruction Cycle]  Execution Cycle Once the opcode is in the IR, the execution cycle is performed. Control circuitry interprets the opcode and execute the instruction by sending out the appropriate control signals to cause data to be moved or an operation to be performed by the ALU.

IAS - Instruction Set IAS instruction set contains 21 instructions [Table 2.1] Can be grouped into the following categories  Data Transfer  Unconditional Branch  Conditional Branch  Arithmetic  Address modify

IAS - Instruction Set Data Transfer Instructions: move data between memory and ALU registers or between two ALU registers. Unconditional Branch Instructions: Normally, the control unit executes instructions in sequence from memory. This sequence can be changed by a branch instruction. This facilitate repetitive operations.

IAS - Instruction Set Conditional Branch Instructions: The branch can be made dependent on a condition, thus allowing decision points. Arithmetic: operations performed by the ALU. Address Modify Instructions: permits addresses to be computed in the ALU and then inserted into instructions stored in memory. This allows considerable addressing flexibility.

Commercial Computers  Eckert-Mauchly Computer Corporation  Their first successful commercial machine was UNIVAC I (Universal Automatic Computer)  It was commissioned by US Bureau of Census 1950 calculations  Eckert-Mauchly Computer Corporation became part of Sperry-Rand Corporation in 1950s  Late 1950s - UNIVAC II —Faster —More memory

IBM  Punched-card processing equipment  the 701  IBM’s first stored program computer  Scientific calculations  the 702  Business applications  Lead to 700/7000 series