ELEN 468 Lecture 171 ELEN 468 Advanced Logic Design Lecture 17 Midterm1 Review

ELEN 468 Lecture 172 Description Styles Explicit structural Implicit structural Explicit continuous assignment Implicit continuous assignment Data flow/RTL Algorithm-based Structural Behavioral

ELEN 468 Lecture 173 Simulation without Delay A = x B = x C = x D = x A = 1 B = 0 C = 0 D = 1 B = 1 C = 1 D = 0 A = 0 C = 0 D = 1 B = 0 t sim B A C D B A CD X X X XY

ELEN 468 Lecture 174 Simulation with Delay A = x B = x C = x D = x A = 1 B = 0 C = 0 D = 1 B = 1 C = 1 D = 0 A = 0 C = 0 D = 1 B = 0 t sim B A C D B A C D X X X X

ELEN 468 Lecture 175 Inertial Delay Delay is caused by charging and discharging node capacitors in circuit Gate delay and wire delay Pulse rejection If pulse with is less than delay, the pulse is ignored B A CD

ELEN 468 Lecture 176 Example of De-scheduling A=x B=x C=x D=x A=1 B=0 C=1D=0 B=1 A=0 C=0 C=1 D=1 A B C D B A C D 32 T_sim

ELEN 468 Lecture 177 Variables Represent values of signals in physical circuit in a digital format Nets – Represent physical connectivity Registers – Abstractions of storage elements Nets and registers may be either scalars or vectors

ELEN 468 Lecture 178 Direct Substitution of Parameters module modXnor(y, a, b); parameter size=8, delay=15; output [size-1:0] y; input [size-1:0] a, b; wire [size-1:0] #delay y = a~^b; endmodule module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor #(4,5) G2(y2, b2, c2); endmodule module modXnor(y, a, b); parameter size=8, delay=15; output [size-1:0] y; input [size-1:0] a, b; wire [size-1:0] #delay y = a~^b; endmodule module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor #(4,5) G2(y2, b2, c2); endmodule Value of a constant can be changed during compliation Don’t confuse with assigning delay to primitives Module instantiation do not have delay Primitives do not have parameters

ELEN 468 Lecture 179 UDP: Combinational Behavior primitive mux_prim ( out, select, a, b ); outputout; inputselect, a, b; table // selecta b: out 00 0: 0;// Each column -> a port 00 1: 0;// Last column -> single output 00 x: 0;// Input port column order = port list order 01 0: 1;// No inout port 01 1: 1;// Only 0, 1, x on input and output 01 x: 1;// A “z” input is treated as “x” 10 0: 0;// If an input vector is not in table, output -> “x” 11 0: 0; 1x 0: 0; 10 1: 1; 11 1: 1; 1x 1: 1; x0 0: 0;// Reduce pessimism x1 1: 1;// Without these 2 rows, output “x” for select = “x” endtable endprimitive mux_prim select out a b

ELEN 468 Lecture 1710 Edge-sensitive Behavior primitive d_flop( q, clock, d ); outputq; inputclock, d; regq; table // clockdstateq/next_state (01)0 :? :0;// Parentheses indicate signal transition (01)1 :? :1;// Rising clock edge (0?)1 :1 :1; (0?)0 :0 :0; (?0)? :? :-;// Falling clock edge ?(??) :? :-;// Steady clock endtable endprimitive clock dq d_flop

ELEN 468 Lecture 1711 Delay Models Gate delay Intrinsic delay Layout-induced delay due to capacitive load Waveform slope-induced delay Net delay/transport delay Signal propagation delay along interconnect wires Module path delay Delay between input port and output port

ELEN 468 Lecture 1712 Gate Delay and (yout, x1, x2);// default, zero gate delay and #3 (yout, x1, x2);// 3 units delay for all transitions and #(2,3) G1(yout, x1, x2); // rising, falling delay and #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4); // Multiple instances a_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoff bufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable); // min:typ:max / rise, fall, turnoff and (yout, x1, x2);// default, zero gate delay and #3 (yout, x1, x2);// 3 units delay for all transitions and #(2,3) G1(yout, x1, x2); // rising, falling delay and #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4); // Multiple instances a_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoff bufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable); // min:typ:max / rise, fall, turnoff Simulators simulate with only one of min, typ and max delay values Selection is made through compiler directives or user interfaces Default delay is typ delay

ELEN 468 Lecture 1713 Example of Time Scale `timescale 1 ns / 10 ps module modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2 ); endmodule `timescale 10 ns / 10 ns module modB(); … … modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin #5 x1 = 0; x2 = 0; #5 x2 = 1; #5 x1 = 1; #5 x2 = 0; end endmodule `timescale 1 ns / 10 ps module modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2 ); endmodule `timescale 10 ns / 10 ns module modB(); … … modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin #5 x1 = 0; x2 = 0; #5 x2 = 1; #5 x1 = 1; #5 x2 = 0; end endmodule $t$real_tx1x2y x1=xx2=xy=x x1=0x2=0y=x x1=0x2=0y= x1=0x2=1y= x1=1x2=1y= x1=1x2=1y= x1=1x2=0y= x1=1x2=0y=1

ELEN 468 Lecture 1714 Simple Module Path Source of path must be a net declared as input or output Destination of path must be a net or reg declared as output or inout Parallel paths, “=>” Full connection paths, “*>”

ELEN 468 Lecture 1715 Example of Simple Module Path Delay module nand1( out, A, B ); outputout; inputA, B; nand ( out, A, B ); specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 ); // 0->1, 1->0, 0->z, z->1, 1->z, z->0 endspecify endmodule module nand1( out, A, B ); outputout; inputA, B; nand ( out, A, B ); specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 ); // 0->1, 1->0, 0->z, z->1, 1->z, z->0 endspecify endmodule A B out Specify blocks declare paths Its path can override structural delays

ELEN 468 Lecture 1716 Combinational Logic Delay Combinational logic delay <= clock period Combinational Logic Register Primary Input Register Primary Output clock

ELEN 468 Lecture 1717 Example of Static Timing Analysis Arrival time: input -> output, take max Required arrival time: output -> input, take min Slack = required arrival time – arrival time /4/-3 5/3/-2 4/7/34/7/3 8/8/08/8/0 9/6/-3 20/17/-3 11/11/0 18/18/0 23/20/-3

ELEN 468 Lecture 1718 Assignment Continuous assignment Values are assigned to net variables due to some input variable changes “assign …=… “ Procedural assignment Values are assigned to register variables when certain statement is executed in a behavior Procedural assignment, “=“ Procedural continuous assignment, “assign …=… [deassign] “ Non-blocking assignment, “<=“

ELEN 468 Lecture 1719 Blocking and Non-blocking Assignment initial begin a = 1; b = 0; a = b; // a = 0; b = a; // b = 0; end initial begin a = 1; b = 0; a <= b; // a = 0; b <= a; // b = 1; end Blocking assignment “=“ Statement order matters A statement has to be executed before next statement Non-blocking assignment “<=“ Concurrent assignment Normally the last assignment at certain simulation time step If it triggers other blocking assignments, it is executed before the blocking assignment it triggers If there are multiple non-blocking assignments to same variable in same behavior, latter overwrites previous

ELEN 468 Lecture 1720 Procedural Continuous Assignment Continuous assignment establishes static binding for net variables Procedural continuous assignment (PCA) establishes dynamic binding for variables “assign … deassign” for register variables only “force … release” for both register and net variables

ELEN 468 Lecture 1721 “assign … deassign” PCA Binding takes effect when PCA statement is executed Can be overridden by another PCA statement “deassign” is optional “assign” takes control, “deassign” release control module flop ( q, qbar, preset, clear, clock, data ); … assign qbar = q; initial q = 0; ( negedge clk ) q = data; ( clear or preset ) begin if ( !preset ) assign q = 1; else if ( !clear ) assign q = 0; else deassign q; end endmodule module flop ( q, qbar, preset, clear, clock, data ); … assign qbar = q; initial q = 0; ( negedge clk ) q = data; ( clear or preset ) begin if ( !preset ) assign q = 1; else if ( !clear ) assign q = 0; else deassign q; end endmodule

ELEN 468 Lecture 1722 Example of assign module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out, reg y_out; begin if (select == 0) assign y_out=a; else if (select == 1) assign y_out=b; else if (select == 2) assign y_out=c; else if (select == 3) assign y_out=d; else assign y_out=1’bx; end endmodule module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out, reg y_out; begin if (select == 0) assign y_out=a; else if (select == 1) assign y_out=b; else if (select == 2) assign y_out=c; else if (select == 3) assign y_out=d; else assign y_out=1’bx; end endmodule y_out changes with a;

ELEN 468 Lecture 1723 Alternative module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out, reg y_out; or a or b or c or d) begin if (select == 0) y_out=a; else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1’bx; end endmodule module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out, reg y_out; or a or b or c or d) begin if (select == 0) y_out=a; else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1’bx; end endmodule Value of ‘a’ is assigned to y_out at this time

ELEN 468 Lecture 1724 Example initial begin a = #10 1; b = #2 0; c = #3 1; end initial begin d <= #10 1; e <= #2 0; f <= #3 1; end initial begin a = #10 1; b = #2 0; c = #3 1; end initial begin d <= #10 1; e <= #2 0; f <= #3 1; end t a b c d e f 0 x x x x x x 2 x x x x 0 x 3 x x x x x x x

ELEN 468 Lecture 1725 Tell the Differences (a or b) y = a|b; (a or b) #5 y = a|b; (a or b) y = #5 a|b; (a or b) y <= #5 a|b; (a or b) y = a|b; (a or b) #5 y = a|b; (a or b) y = #5 a|b; (a or b) y <= #5 a|b; Event control is blocked Which one describes or gate?

ELEN 468 Lecture 1726 Parallel Activity Flow … fork // t_sim = 0 #50 wave = 1; #100 wave = 0; #150 wave = 1; #300 wave = 0; // executes at t_sim = 300 join … fork // t_sim = 0 #50 wave = 1; #100 wave = 0; #150 wave = 1; #300 wave = 0; // executes at t_sim = 300 join … module race ( … ); … fork #150 a = b; #150 c = a; join endmodule module fix_race ( … ); … fork a = #150 b; c = #150 a; join endmodule module race ( … ); … fork #150 a = b; #150 c = a; join endmodule module fix_race ( … ); … fork a = #150 b; c = #150 a; join endmodule Not supported by synthesis For simulation in testbench

ELEN 468 Lecture 1727 Tasks and Functions Sub-programs that encapsulate and organize a description Tasks – create a hierarchical organization of the procedural statements Functions – substitute for an expression

ELEN 468 Lecture 1728 SetupHold $setuphold(data, posedge clock, 5, 2); 5 5 clock data 22

ELEN 468 Lecture 1729 Finite State Machines Next state and output Combinational logic Next state and output Combinational logic Register clock inputoutput Next state Combinational logic Next state Combinational logic Register Output Combinational logic Output Combinational logic input output clock Mealy Machine Moore Machine

ELEN 468 Lecture 1730 Explicit Finite State Machines 1 module FSM_style1 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; assign outputs = …; // function of state and inputs assign next_state = …; // function of state and inputs ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule module FSM_style1 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; assign outputs = …; // function of state and inputs assign next_state = …; // function of state and inputs ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule

ELEN 468 Lecture 1731 Explicit Finite State Machines 2 module FSM_style2 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; assign outputs = …; // function of state and inputs ( state or inputs ) begin // decode for next_state with case or if statement end ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule module FSM_style2 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; assign outputs = …; // function of state and inputs ( state or inputs ) begin // decode for next_state with case or if statement end ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule

ELEN 468 Lecture 1732 Explicit Finite State Machines 3 module FSM_style3 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; ( state or inputs ) begin // decode for next_state with case or if statement end ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else begin state <= next_state; outputs <= some_value ( inputs, next_state ); end endmodule module FSM_style3 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; ( state or inputs ) begin // decode for next_state with case or if statement end ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else begin state <= next_state; outputs <= some_value ( inputs, next_state ); end endmodule

ELEN 468 Lecture 1733 FSM Example: Speed Machine speed accelerator brake clock medium lowstopped high a: accelerator b: brake a = 1, b = 0 b = 1 a = 1, b = 0

ELEN 468 Lecture 1734 Implicit Finite State Machine module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 ( posedge clock ) if ( brake == 1`b1 ) case ( speed ) `stopped: speed <= `stopped; `low: speed <= `stopped; `medium: speed <= `low; `high: speed <= `medium; default: speed <= `stopped; endcase else if ( accelerator == 1`b1 ) case ( speed ) `stopped: speed <= `low; `low: speed <= `medium; `medium: speed <= `high; `high: speed <= `high; default: speed <= `stopped; endcase endmodule ( posedge clock ) if ( brake == 1`b1 ) case ( speed ) `stopped: speed <= `stopped; `low: speed <= `stopped; `medium: speed <= `low; `high: speed <= `medium; default: speed <= `stopped; endcase else if ( accelerator == 1`b1 ) case ( speed ) `stopped: speed <= `low; `low: speed <= `medium; `medium: speed <= `high; `high: speed <= `high; default: speed <= `stopped; endcase endmodule

ELEN 468 Lecture 1735 Pull Gates module nmos_nand_2 ( Y, A, B ); output Y; input A, B; supply0 GND; tri w; pullup ( Y ); nmos ( Y, w, A ); nmos ( w, GND, B ); endmodule module nmos_nand_2 ( Y, A, B ); output Y; input A, B; supply0 GND; tri w; pullup ( Y ); nmos ( Y, w, A ); nmos ( w, GND, B ); endmodule Y V dd A B

ELEN 468 Lecture 1736 Assign Drive Strengths nand ( pull1, strong0 ) G1( Y, A, B ); wire ( pull0, weak1 ) A_wire = net1 || net2; assign ( pull1, weak0 ) A_net = reg_b; nand ( pull1, strong0 ) G1( Y, A, B ); wire ( pull0, weak1 ) A_wire = net1 || net2; assign ( pull1, weak0 ) A_net = reg_b; Drive strength is specified through an unordered pair one value from { supply0, strong0, pull0, weak0, highz0 } the other from { supply1, strong1, pull1, weak1, highz1 } Only scalar nets may receive strength assignment When a tri0 or tri1 net is not driven, it is pulled to indicated logic value with strength of pull0 or pull1 The trireg net models capacitance holds a charge after the drivers are removed, the net has a charge strength of small, medium(default) or large capacitor

ELEN 468 Lecture 1737 StL PuH Ambiguous Control Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 x bufif0 St0 x bufif0 Pu1

ELEN 468 Lecture 1738 Strength Reduction Dependence of output strength on input strength Combinational and pull gate – NO, except 3-state gates Transistor switch and bi-directional gates – YES In general, output strength <= input strength

ELEN 468 Lecture 1739 Signal Contention: Known Strength and Known Value Signal with greater strength dominates Same strength, different logic values wand -> and, wor -> or Otherwise -> x driver1 driver2 We0 Pu1

ELEN 468 Lecture 1740 Example of Rule 1 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 signal1signal2 result Rule 1: Include strengths of ambiguous signal that greater than strength of unambiguous signal

ELEN 468 Lecture 1741 Example of Rule 2 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 signal1signal2 result Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Rule 2: Omit strengths of ambiguous signal <= strength of unambiguous signal, except Rule 3

ELEN 468 Lecture 1742 Example of Rule 3 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su1 St1 Pu1 La1 We1 Me1 Sm1 HiZ1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 signal2 result signal1 Su0 St0 Pu0 La0 We0 Me0 Sm0 HiZ0 Rule 3: If unambiguous and ambiguous signals have different values, take strengths range from Rule1 to strength of unambiguous signal

ELEN 468 Lecture 1743 Logic Synthesis Translation Engine Optimization Engine Mapping Engine Behavioral Descriptions Technology Libraries Two-level Logic Functions Optimized Multi- level Logic Functions Technology Implementation

ELEN 468 Lecture 1744 Objective of Synthesis Area Delay

ELEN 468 Lecture 1745 General Rules for Combinational Logic Avoid to model specific technology Synthesis functionality Ignore timing Avoid feedback loops Feedback loop may result in sequential circuit

ELEN 468 Lecture 1746 Simulation Efficiency and PCA module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; (en or a or b or c or d ) y = ~( en & (a | b) & (c | d) ); endmodule module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; (en or a or b or c or d ) y = ~( en & (a | b) & (c | d) ); endmodule module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; ( en ) if ( en ) assign y = ~((a|b) & (c|d)); else assign y = 1; endmodule module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; ( en ) if ( en ) assign y = ~((a|b) & (c|d)); else assign y = 1; endmodule Less efficient Generally, PCA is efficient on implementing combinational logic in behavioral descriptions Keyword deassign is only used in sequential circuits.

ELEN 468 Lecture 1747 Example of Unwanted Latch module myMux( y, selA, selB, a, b ); input selA, selB, a, b; output y; reg y; ( selA or selB or a or b ) case ( {selA, selB} ) 2’b10: y = a; 2’b01: y = b; endcase endmodule module myMux( y, selA, selB, a, b ); input selA, selB, a, b; output y; reg y; ( selA or selB or a or b ) case ( {selA, selB} ) 2’b10: y = a; 2’b01: y = b; endcase endmodule b a selA’ selB selA selB’ latch y en