CprE566 / Fall 06 / Prepared by Chris ChuPartitioning1 CprE566 Partitioning

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning2 System Hierarchy

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning3 Why do we need a hierarchy? Subsystems can be designed independently and simultaneouslySubsystems can be designed independently and simultaneously Flexibility of changing part of the systemFlexibility of changing part of the system Reduced design complexity for smaller subsystemsReduced design complexity for smaller subsystems

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning4 Levels of Partitioning System Level Partitioning Board Level Partitioning Chip Level Partitioning System PCBs Chips Subcircuits / Blocks

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning5 Objectives and Constraints Objectives:Objectives: –Interconnections between partitions –Delay due to partitioning Constraints:Constraints: –Number of terminals –Area / Size of each partition –Number of partitions

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning6 Some Terminologies Partitioning: Dividing into a small number of partitions. Clustering: Dividing into a large number of small partitions. Covering / Technology Mapping: Clustering such that each partitions (clusters) have some special structure (e.g., can be implemented by a cell in a cell library). k-way Partitioning: Dividing into k partitions. Bipartitioning: 2-way partitioning. Bisectioning: Bipartitioning such that the two partitions have the same size.

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning7 Partitioning of a Circuit

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning8 Circuit Representation Netlist:Netlist: –Gates: A, B, C, D –Nets: {A,B,C}, {B,D}, {C,D} Hypergraph:Hypergraph: –Vertices: A, B, C, D –Hyperedges: {A,B,C}, {B,D}, {C,D} –Vertex label: Gate size –Hyperedge label: Importance of net A B CD A B C D

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning9 A Useful Survey Paper Charles Alpert and Andrew Kahng, “Recent Directions in Netlist Partitioning: A Survey”, Integration: the VLSI Journal, 19(1-2), 1995, pp Charles Alpert and Andrew Kahng, “Recent Directions in Netlist Partitioning: A Survey”, Integration: the VLSI Journal, 19(1-2), 1995, pp

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning10 Logic Hierarchy Guided Partitioning Y. Cheon and D. F. Wong, “Design Hierarchy Guided Multilevel Circuit Partitioning”, ISPD 2002.Y. Cheon and D. F. Wong, “Design Hierarchy Guided Multilevel Circuit Partitioning”, ISPD –Multilevel partitioning approach –Design hierarchy provides useful guidance in clustering –However, elements in design hierarchy may not be strongly connected –Use Rent’s rule to identify hierarchy elements with strong connectivity –Significantly better cut size and similar runtime to hMETIS

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning11 Logic Hierarchy May Not be Suitable Three designs by IBM in the next three slidesThree designs by IBM in the next three slides J. Cong, “Timing Closure Based on Physical Hierarchy”, ISPD-2002.J. Cong, “Timing Closure Based on Physical Hierarchy”, ISPD –Suggests to flatten the logic hierarchy and build a physical hierarchy instead RT-level Floorplan verses Mixed-Mode PlacementRT-level Floorplan verses Mixed-Mode Placement

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning12 Hierarchy Example Plots

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning13 Hierarchy Example Plots

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning14 Hierarchy Example Plots

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning15 Kernighan-Lin Algorithm “An Efficient Heuristic Procedure for Partitioning Graphs” The Bell System Technical Journal 49(2): , 1970

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning16 Problem Solved Restrictions:Restrictions: –For Bisectioning of circuit. –Assume all gates are of the same size. –Works only for 2-terminal nets. If all nets are 2-terminal,If all nets are 2-terminal, the Hypergraph is called a Graph. A B C D Hypergraph Representation Graph Representation A B C D

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning17 Problem Formulation Input: A graph withInput: A graph with –Set vertices V. (|V| = 2n) –Set of edges E. (|E| = m) –Cost c AB for each edge {A, B} in E. Output: 2 partitions X & Y such thatOutput: 2 partitions X & Y such that –Total cost of edges cut is minimized. –Each partition has n vertices. This problem is NP-Complete!!!!!This problem is NP-Complete!!!!!

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning18 A Trivial Approach Try all possible bisections. Find the best one.Try all possible bisections. Find the best one. If there are 2n vertices,If there are 2n vertices, # of possibilities = 2n C n /2 = (2n)! / 2n! 2 = n O(n) For 4 vertices (A,B,C,D), 3 possibilities.For 4 vertices (A,B,C,D), 3 possibilities. 1. X={A,B} & Y={C,D} 2. X={A,C} & Y={B,D} 3. X={A,D} & Y={B,C} For 100 vertices, 5x10 28 possibilities.For 100 vertices, 5x10 28 possibilities. Need 1.59x10 13 years if one can try 100M possbilities per second.Need 1.59x10 13 years if one can try 100M possbilities per second.

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning19 Idea of KL Algorithm D A = Decrease in cut value if moving A.D A = Decrease in cut value if moving A. If switch A & B, gain(A,B) = D A +D B -2c ABIf switch A & B, gain(A,B) = D A +D B -2c AB A B C D XY A B C D XY D A = 2-1 = 1 D B = 1-1 = 0 A B C D XY A B C D XY gain(A,B) = = -1

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning20 Idea of KL Algorithm Start with any initial partitions X and Y.Start with any initial partitions X and Y. A pass (exchanging each vertex exactly once) is described below:A pass (exchanging each vertex exactly once) is described below: 1. For i := 1 to n do From the unlocked (unexchanged) vertices, From the unlocked (unexchanged) vertices, choose a pair (A,B) s.t. gain(A,B) is largest. choose a pair (A,B) s.t. gain(A,B) is largest. Exchange A and B. Lock A and B. Exchange A and B. Lock A and B. Let g i = gain(A,B). Let g i = gain(A,B). 2. Find the k s.t. G=g g k is maximized. 3. Switch the first k pairs. Repeat the pass until there is no improvement (G=0).Repeat the pass until there is no improvement (G=0).

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning21 Example 1 X Y Original Cut Value = 9 4 X Y Optimal Cut Value = 5

CprE566 / Fall 06 / Prepared by Chris ChuPartitioning22 Time Complexity of KL For each pass,For each pass, –O(n 2 ) time to find the best pair to exchange. –n pairs exchanged. –Total time is O(n 3 ) per pass. Better implementation can get O(n 2 log n) time per pass.Better implementation can get O(n 2 log n) time per pass. Number of passes is usually small.Number of passes is usually small.