Trigger Workshop: Greg Iles Feb Optical Global Trigger Interface Card Dual CMC card with Virtex 5 LX110T 16 bidirectional 3.2Gb/s optical links 320 conventional I/O

Trigger Workshop: Greg Iles Feb Introduction RCT to GCT Links: Optical links based on 8B/10B GCT to GT Links: Legacy links from old GCT project DC coupled electrical links –Legacy links from GCT to GT were retained in the revised GCT. –Ensured that GCT-GT interface remained the same –Copper high speed links based on National Semiconductor DS92LV16 –However, links not robust –System in USC55 works, but precarious

Trigger Workshop: Greg Iles Feb Optical Global Trigger Interface Virtex5-110T> 320 configurable I/O Two I/O bank voltages 4x Bidirectional POP4s 3.2 Gb/s at 150m Use same card for Tx at GCT and Rx at GT

Trigger Workshop: Greg Iles Feb Optical Global Trigger Interface –Upgraded links to match those between RCT and GCT, albeit based on Xilinx Virtex5-110T FPGA allows flexibility –Can change link speed/protocol easily FPGA provides 16 channels at 3.7Gb/s, –Current POP4 fibre optic transceivers limited to 3.2Gb/s –Optical Global Trigger Interface Running asynchronously at 3Gb/s on all 16 channels Protected with CRC Check Automatic link configuration to correct latency –System currently designed to match current requirements Option to increase bandwidth into GT by factor of >2

Trigger Workshop: Greg Iles Feb Asynchronous 3Gb/s links 80MHz Low Latency Clock Domain Bridge Fifo / DualPort RAM remove ‘extra’ comma remove enable Add CRC 3.0 Gb/s 80MHz Check CRC Gigabit Transceiver - TxGigabit Transceiver - Rx Data & 150MHz from Osc-1 Data & 150MHz from Osc-2 Automatic latency synchronisation: Loop over all Fifo locations until Trigger Path BC0 arrives with fixed discrepancy relative to TTC BC0 TTC BC0

Trigger Workshop: Greg Iles Feb Latency: Clk80 to Clk80 data All numbers in bxVirtex5 3.0Gb/s Bridge from LHC 80MHz to link clock0.5 (e) Serdes Tx-Rx Delays (datasheet)2.7 (d) Elastic Buffer (5x3.3ns) + Timing Reg (3.3ns)0.8 (g) Bridge from link clock to LHC 80MHz clock1.4 (c) Total (theory)5.4 Total (practice)5.5 Notes: (a) Latency calculated from clk edge sampling data into SerDes until clk edge exiting SerDes (b) The numbers are obtained from simulation/datasheets and theoretical performance. (c) Assumed 1 write clks (300MHz), 5 read clks (160MHz), If data aligned to slower clock then wait for 1 slow clk to collect all data and up to 1 slow clock to align to slower clock (d) No elastic buffer. Tx = 9.5 x RXUSRCLK, Rx = 10.5 RXUSRCLK (e) Currently bridges from 80MHz to 150MHz in word mode (byte mode would be slightly better). (f) All numbers worst case, but no contingency. (g) Elastic buffer could be removed, albeit with some extra complexity in the VHDL.

Trigger Workshop: Greg Iles Feb Matrix Card Matrix Card compatibility –Drop In Code –OGTI card and Matrix card both use Xilinx Virtex5 LX11 0T –Current links use existing GCT protocol. May want to change for SLHC.

Trigger Workshop: Greg Iles Feb Quiet Regions & MIP bits

Trigger Workshop: Greg Iles Feb Old Design: Quiet Regions & MIP bits RCT GCT:Source Cards (ECL to optical fibre) GCT:Main Crate (Data processing) GT PSB GTI GMT PSB RPC/CSC/DT uTCA Crate (3x Matrix & CopperLink card)

Trigger Workshop: Greg Iles Feb New Design: Quiet Regions & MIP bits RCT GCT:Source Cards (ECL to optical fibre) GCT:Main Crate (Data processing) GT PSB-O OGTI GMT PSB-O RPC/CSC/DT

Trigger Workshop: Greg Iles Feb GCT-GT links –Ran all 16 links overnight using different Rx/Tx 100MHz oscillators No errors ~ bits –Integrated into GCT hardware –Vienna about to manufacture a new PSB to provide an interface to the GT. –Ready to manufacture final boards

Trigger Workshop: Greg Iles Feb Extra

Trigger Workshop: Greg Iles Feb Latency All numbers in bxCurrent Design Virtex5 1.6Gb/s Virtex5 2.4Gb/s Virtex5 3.2Gb/s Virtex5 3.0Gb/s Send 2 nd word0.5 IOB and 80MHz->LinkWordSpeed (e)0.9 (e)0.8 (e)0.9 Serdes Tx-Rx Delays (datasheet) (d)3.3 (d)2.5 (d)2.7 (d) Cable/Fibre (1.5m). Now 2m Serdes to FPGA Elastic Buffer (5x3.3ns) + Timing Reg (3.3ns) Sync to Local LHC clk (c) 1.6 Total Latency increase comparted to TDR Link(3bx) + Sync(1.5bx) = 4.5bx Notes: (a) Latency calculated from clk edge sampling data into SerDes/FPGA until FPGA fabric (b) The numbers are obtained from datasheets and theoretical performace. (c) Assumed 1.0 bx here, but could be 2.0 depending on sync method. (d) No elastic buffer. Tx = 9.5 x RXUSRCLK, Rx = 10.5 RXUSRCLK (e) Assumed ¼ bx for IOB + 2 link speed clks (4 x ½). Based on current 80MHz to 100MHz bridge. (f) All numbers worst case, but no contingency. (g) block ram performance dependent. BaselineCurrent

Trigger Workshop: Greg Iles Feb PCB Used 14 layers simply to make routing easier > 320 I/O Routing high speed differential pairs was not that nice.