Data/Frame Memory PE 0 PE 1 PE 2 PE 3 PE N … Control Instruction Memory Interconnect The SIMD Concept.

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Presentation transcript:

Data/Frame Memory PE 0 PE 1 PE 2 PE 3 PE N … Control Instruction Memory Interconnect The SIMD Concept

Embedded Computer Architecture 5KK73 TU/e Henk Corporaal Bart Mesman SIMD: XETAL and IMAP

Xetal-II Philips, NXP, TU/e

XETAL-II SRAM 8051 ZigBee CPLD Xetal-II

600 mW 90 nm CMOS 53.5 GOPS (arithmetic 84MHz Best computational efficient programmable silicon in 2007 [Kleihorst, et al.2007] GPO Out I2CI2C GPI Program (16k x 56b) Data (2k x 16b) Linear Processor Array (320 PEs) Sequential I/O Memory (2 lines x 320 words) DIP DOP Frame Memory (2048 lines x 320 words) IMEM (240 kb) OMEM,LUT (240 kb) In Xetal-II Processor

All PEs access the same line of the Frame Memory Xetal-II Memory Access

Integrated Memory Array Processor IMAP (NEC)

IMAP-CE IMAP-1 IMAP-VISION MHz, 32PE/Chip 15MHz, 8PE /Chip Peak Performance(GOPS) 100MHz, 128PE/Chip 4-Way VLIW,50GOPS 0.18um, 2 ～ 4Watt IMAP-2 40MHz, 64PE/Chip IMAPCAR 100MHz, 128PE/Chip 4-Way VLIW+MAC, 100GOPS (-40 ℃～ 85 ℃ ), 0.13 um, <2Watt 1000 IMAP Series Processors (NEC) ISSCC’03 ISSCC’95 Year 11.0mm PE8 CP EXTIF DPLL IMAP-CE( 32.7M Tr, 0.18um ) (PE8: eight PEs integration block) CAMP’97 [Shorin Kyo, et al.2005]

IMAPCAR Block Diagram and Features Video IN Video OUT P$,D$,STK RAM EMEM Host Processor Control Processor (CP) 4 Way VLIW PE SR0 SR1 SR2 IMEM External Mem. I/F 12.8 GByte/s 0.8 GByte/s SR3 128 EMEM ADD MUL RDU 24 x 8b General Purpose Registers To/Fr other PEs To/Fr IMEM LSU COMM To/Fr CP LOG 4)128 individual RAM blocks 1)128 4-Way VLIW PEs 2)< 100MHz 3)130nm CMOS ALUx1,MULx1,LOGx1,LSUx1

IMAPCAR Memory Access: local addressing support Each PE could access different lines of the Memory Requires separate memory module per PE

IMAPCAR2: XC core (NEC)

XC Core: SIMD/MIMD 90nm CMOS, 108MHz [Shorin Kyo, et al.2009]

XC Core: SIMD Mode

XC Core: MIMD Support

4 SIMD PE -> 1 MIMD FPU

Xetal-Pro TU/e : 2010

Xetal-Pro Memory Access All PEs access the same line of the Scratchpad Memory or Frame Memory Characteristics: 1)320 single-issue PEs 125MHz 3)65nm CMOS 4)1pJ/op at sub- threshold