DSP/BIOS System Integration Workshop Copyright © 2004 Texas Instruments. All rights reserved. T TO Technical Training Organization 1 1.Introduction 2.Real-Time System Design Considerations 3.Hardware Interrupts (HWI) 4.Software Interrupts (SWI) 5.Task Authoring (TSK) 6.Data Streaming (SIO) 7.Multi-Threading (CLK, PRD) 8.BIOS Instrumentation (LOG, STS, SYS, TRC) 9.Static Systems (GCONF, TCONF) 10.Cache (BCACHE) 11.Dynamic Systems (MEM, BUF) 12.Flash Programming (HexAIS, Flashburn) 13.Inter-Thread Communication (MSGQ,...) 14.DSP Algorithm Standard (XDAIS) 15.Input Output Mini-Drivers (IOM) 16.Direct Memory Access (DMA) 17.Review

Learning Objectives  Describe the basic concepts of SWIs  Demonstrate how to post a SWI  Describe the SWI object  List other SWI post options  Show how QUEues pass data between threads  Add a SWI to an HWI-based system T TO Technical Training Organization 2

HWI SWI 2 SWI 1 IDL time Highest Priority Lowest Priority Running Ready T TO Technical Training Organization Software Interrupts  Concepts  Posting a SWI  SWI Object  Other SWI Posts  Queues - QUE  Lab 3

New Paradigm: DSP/BIOS Scheduler main() { init while(1) if(flag=1) process printf() other... }  SWI_post is equivalent to setting ISR flag  Scheduler replaces the while loop  SWI manager is like ‘if’ test with no overhead ISR get buffer flag =1 main() { init } SWI filter LOG_printf() HWI get buffer SWI_post IDL other + instrumentation BIOS Scheduler T TO Technical Training Organization 4

Hardware and Software Interrupt System T TO Technical Training Organization HWI  Fast response to interrupts  Minimal context switching  High priority for CPU  Limited number of HWI possible SWI  Latency in response time  Context switch performed  Selectable priority levels  Execution managed by scheduler  DSP/BIOS provides for HWI and SWI management  DSP/BIOS allows the HWI to post an SWI to the ready queue Execution flow for flexible real-time systems: INT ! Hard R/T Process Post SWI Cleanup, RETURN Continue Soft R/T Processing... SWI Ready HWI SWI { *buf++ = *SPRR; count--; if (count = = 0) { SWI_post(&swiFir); count = COUNT; buf = &buf2; } 5

DSP/BIOS Preemptive Scheduler Hardware Interrupts (HWI)  Urgent response time  Often at “sample rate”  Microseconds duty cycle  Preemptive or non-preemptive Software Interrupts (SWI)  Flexible processing time  Often at “frame rate”  Milliseconds duty cycle  Preemptive Idle (IDL)  Best Effort  Sequential Execution SWI_ post() Foreground Background Hard Real-time Soft Real-time T TO Technical Training Organization 6

HWI SWI IDL BIOS: Prioritized Scheduling Highest Priority Lowest Priority  HWICollect data into frame/buffer, perform minimum processing  SWIProcess each datum in buffer  IDLRuns when no real-time events are active  HWI preempt SWI - new data is not inhibited by processing of frame Running Ready Legend Collect SamplesPost SWIProcess Buffer time T TO Technical Training Organization 7

State Diagrams: IDL, HWI, SWI  IDL  Lowest priority - soft real-time - no deadline  Idle functions executes sequentially  Priority at which real-time analysis is passed to host  HWI & SWI  Encapsulations of functions with priorities managed by DSP/BIOS kernel  Run to completion (cannot be suspended or terminated prior to completion)  Runs only once regardless of how many times posted prior to execution Return from main( ) InactiveReadyRunning Started Resume Preempted Started Resume InactiveReady Running Completed Posted Preempted Created T TO Technical Training Organization 8

HWI SWI 2 SWI 1 IDL time Highest Priority Lowest Priority Running Ready T TO Technical Training Organization Software Interrupts  Concepts  Posting a SWI  SWI Object  Other SWI Posts  Queues - QUE  Lab 9

HWI SWI_a (p1) IDL SWI_b (p2) Scheduling Rules Highest Priority Lowest Priority Running Ready Legend  SWI_post(&mySwi) : Unconditionally post a software interrupt (in the ready state)  If a higher priority thread becomes ready, the running thread is preempted  SWI priorities from 1 to 14  Automatic context switch (uses system stack) time SWI_post( &SWI_b ) T TO Technical Training Organization 10

HWI SWI_a (p1) IDL SWI_b (p1) Scheduling Rules Highest Priority Lowest Priority Running Ready Legend  Processes of same priority are scheduled first-in first-out time SWI_post( &SWI_b ) T TO Technical Training Organization 11

HWI SWI_a (p1) IDL SWI_b (p2) Posting a SWI from an HWI Highest Priority Lowest Priority  Problem: Scheduler not aware of interrupt!  If ISR posts a higher priority SWI, the scheduler will run that SWI in the context of the HWI - not usually desired Running Ready Legend SWI_post( &SWI_b ) time ? T TO Technical Training Organization 12

HWI SWI_a (p1) IDL SWI_b (p2) Using the Dispatcher with HWI Highest Priority Lowest Priority  Solution: Use the Dispatcher  Some APIs that may affect scheduling: SWI_post, SWI_andn, SWI_dec, SWI_inc, SWI_or, SEM_post, PIP_alloc, PIP_free, PIP_get, PIP_put, PRD_tick Running Ready Legend SWI_post() time T TO Technical Training Organization 13

Scheduling Strategies  Most important “Deadline Monotonic”  Assign higher priority to the most important process  Rate monotonic analysis  Assign higher priority to higher frequency events  Events that execute at the highest rates are assigned highest priority  An easy way to assign priorities in a system!  Systems under 69% loaded guaranteed to run successfully (proofs for this in published papers)  Also allows you to determine scheduling bounds  Dynamic priorities  Raise process priority as deadline approaches T TO Technical Training Organization 14

DSP/BIOS: Priority-Based Scheduling HWI 1 HWI 2 SWI 3 SWI 2 SWI 1 MAIN IDLE SWI_post(&swi_name); int2 rtn post2rtn int1 post3rtn post1 rtn Click here to skip animation T TO Technical Training Organization 15

DSP/BIOS: Priority-Based Scheduling T TO Technical Training Organization 16

Another Scheduling Example HWI 1 HWI 2 SWI 3 SWI 2 SWI 1 MAIN IDLE rtn int1 post2rtn post1rtn int2 rtn post2 rtn post3 post1 The BIOS Execution Graph provides this kind of information to assist in temporal debugging T TO Technical Training Organization 17

HWI SWI 2 SWI 1 IDL time Highest Priority Lowest Priority Running Ready T TO Technical Training Organization Software Interrupts  Concepts  Posting a SWI  SWI Object  Other SWI Posts  Queues - QUE  Lab 18

Creation of SWI with Configuration Tool Creating a new SWI 1. right click on SWI mgr 2. select “Insert SWI” 3. type SWI name 4. right click on new SWI 5. select “Properties” 6. indicate desired function priority mailbox value SWI_Obj... fxn priority mailbox arg0 arg1... T TO Technical Training Organization 19

SWI Attributes : Manage SWI Properties  Allows programmer to inspect and modify key SWI object values  Do not modify fields on preempted or ready to run SWI recommended: implement during lower priority thread  Priority range is 1 to 14, inclusive  Example - changing a SWI’s priority to 5 : extern SWI_Obj swiProcBuf; SWI_Attrs attrs; SWI_getattrs (&swiProcBuf, &attrs); attrs.priority = 5; SWI_setattrs (&swiProcBuf, &attrs); fxn arg0 arg1 priority mailbox SWI_Attrs SWI_Obj... fxn priority mailbox arg0 arg1... get set 20

SWI Structures (from swi.h and fxn.h) typedef struct SWI_Attrs { SWI_Fxnfxn; Argarg0; Argarg1; Intpriority; Unsmailbox; } SWI_Attrs; typedef struct SWI_Obj { Intlock; Ptrready; Unsmask; priority Ptrlink; Unsinitkey; reset value for SWI mailbox Unsmailbox; SWI mailbox - used with SWI_or, etc FXN_Objfxnobj; Intstslock; STS_Obj*sts; implicit SWI statistical object } SWI_Obj; typedef struct FXN_Obj { Fxnfxn; Argarg1; Argarg0; } FXN_Obj;  SWI_Attrs contains the most commonly used SWI object elements  SWI_getattrs and SWI_setattrs allow well defined access to these elements  SWI object can be directly access also, if desired, as per these examples: myValue = mySwi.fxnobj.arg1; mySwi.fxnobj.arg0 = 7; T TO Technical Training Organization 21

Managing Thread Priorities via GCONF  Drag-and-drop SWIs in list to vary priority  Priorities range from 1–14  Scheduler is invoked when SWI is posted  When scheduler runs, control is passed to the highest priority thread  Equal priority SWIs run in the order posted T TO Technical Training Organization 22

HWI SWI 2 SWI 1 IDL time Highest Priority Lowest Priority Running Ready T TO Technical Training Organization Software Interrupts  Concepts  Posting a SWI  SWI Object  Other SWI Posts  Queues - QUE  Lab 23

SWI Post and SWI Mailbox Overview  If the value of the mailbox is needed by the SWI, use SWI_getmbox() which returns the value of the mailbox when the SWI was posted.  Note: this is a ‘shadow’ value for use within the SWI – BIOS manages a second mailbox for the next posting of the SWI  After each posting, the mailbox is reset to the initial condition specified in the SWI object Mailbox function Bitmask CounterNot Used Always Post SWI_orSWI_incSWI_post Post on mailbox = 0 SWI_andnSWI_dec T TO Technical Training Organization APIAllows you to : SWI_incKnow how many times the SWI was posted before it ran SWI_decPost N times before the SWI is scheduled – a countdown SWI_orSend a single value to the SWI when posting - signature SWI_andnOnly post the SWI when multiple posters all have posted 24

SWI API Summary SWI_postPost a software interrupt SWI_andnClear bits from SWI's mailbox; post if becomes 0 SWI_orOr mask with value contained in SWI's mailbox field SWI_incIncrement SWI's mailbox value SWI_decDecrement SWI's mailbox value; post if becomes 0 SWI_getattrsCopy SWI attribute from SWI object to a structure SWI_setattrsUpdate SWI object attributes from specified structure SWI_getmboxObtain the value in the mailbox prior to SWI run SWI APIDescription SWI_createCreate a SWI SWI_deleteDelete a SWI SWI_disableDisable software interrupts SWI_enableEnable software interrupts SWI_getpriReturn a SWI’s priority mask SWI_raisepriRaise a SWI’s priority SWI_restorepriRestore a SWI’s priority SWI_selfReturn current SWI’s object handle Mod 11 Mod 7 T TO Technical Training Organization 25

T TO Technical Training Organization Software Interrupts  Concepts  Posting a SWI  SWI Object  Other SWI Posts  Queues - QUE  Lab 26

msg1msg2msg3 QUE_Obj struct MyMessage { QUE_Elem elem; first field for QUE Int x[1000]; array/structure sent not copy based! } Message1; typedef struct QUE_Elem { struct QUE_Elem *next; struct QUE_Elem *prev; } QUE_Elem; typedef struct QUE_Elem { struct QUE_Elem *next; struct QUE_Elem *prev; } QUE_Elem; Queue Concepts  QUE message is anything you like, starting with QUE_Elem  QUE_Elem is a set of pointers that BIOS uses to manage a double linked list  Items queued are NOT copied – only the QUE_Elem ptrs are managed! QUE_put(hQue,*msg3) add message to end of queue ( writer ) *elem = QUE_get(hQue) get message from front of queue ( reader ) msg1msg2msg3 QUE_Obj How do you synchronize reader and writer? T TO Technical Training Organization 27

Queue Usage T TO Technical Training Organization  QUE Properties  any number of messages can be passed  atomic API assure correct sequencing  no intrinsic semaphore  Using QUE  Declare the QUE via the config tool  Define (typedef) the structure to queue – 1 st element must be “QUE_Elem”  Fill the message(s) to QUE with the desired data  Send the data to the queue via QUE_put(&myQue, msg);  Acquire data from the queue via info=QUE_get(&myQue);  Application Considerations  Two queues are needed to circulate messages between two threads typedef struct MsgObj { QUE_Elem elem; short *pInBuf; short *pOutBuf; } MsgObj, *Msg; toDevQ toProcQ SWI put get put HWI Main (init) put

Queue Lab Steps T TO Technical Training Organization 28 GCONF:1. Declare 2 QUEues called toDev and toProc ABOVE MAIN: 2. Declare 2 Input Buffers and 2 Output Buffers 3. Define a message structure to send over the QUEs: - first element of a QUE message must be of type QUE_Elem - 'payload' in this lab will be 2 pointers ( *pIn, *pOut ) 4. Declare, as globals, an array of two messages of the type created above IN MAIN: 5. Initialize the pointers in message 1 to point to in/out buffers 1 6. Initialize the pointers in message 2 to point to in/out buffers 2 7. "Prime" the toDev QUE with the two messages HWI CODING:8. At the top of the HWI, if the current buffer size drops to 0: - get a new message from the toDev QUE - extract the input buffer pointer from the message - extract the output buffer pointer from the message - as before, each time the HWI is posted: - fill 1 new input buffer word - output 1 output buffer word 9. At the bottom of the HWI, if the current buffer is full: - send the message with the current pointer set to the SWI via the toProc QUE - zero the buffer size counter SWI CODING: 10. At the top of the SWI, get a message from the toProc QUE - extract the input buffer pointer from the message - extract the output buffer pointer from the message - as before, FIR filter the input buffer & store results to the output buffer 11. At the end of the SWI, return the message to the HWI via the toDev QUE

QUE API Summary QUE_putAdd a message to end of queue – atomic write QUE_getGet message from front of queue – atomic read QUE_enqueueNon-atomic QUE_put QUE_dequeueNon-atomic QUE_get QUE_headReturns ptr to head of queue (no de-queue performed) QUE_emptyReturns TRUE if queue has no messages QUE_nextReturns next element in queue QUE_prevReturns previous element in queue QUE_insertInserts element into queue in front of specified element QUE_removeRemoves specified element from queue QUE_new…. QUE APIDescription QUE_createCreate a queue QUE_deleteDelete a queue Mod 11 T TO Technical Training Organization 29

HWI SWI 2 SWI 1 IDL time Highest Priority Lowest Priority Running Ready T TO Technical Training Organization Software Interrupts  Concepts  Posting a SWI  SWI Object  Other SWI Posts  Queues - QUE  Lab 30

Block FIR Filter Overview  Read block of data to input buffer A/D SP HWI T TO Technical Training Organization 31

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer A/D SP HWI T TO Technical Training Organization 32

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer A/D SP HWI T TO Technical Training Organization 33

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer  Repeat for BLOCKSIZE iterations A/D SP HWI T TO Technical Training Organization 34

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer  Repeat for BLOCKSIZE iterations A/D SP HWI T TO Technical Training Organization 35

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer  Repeat for BLOCKSIZE iterations A/D SP HWI T TO Technical Training Organization 36

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer  Repeat for BLOCKSIZE iterations A/D SP HWI T TO Technical Training Organization 37

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer  Repeat for BLOCKSIZE iterations  Send output buffer to DAC A/D SP HWI SP D/A HWI T TO Technical Training Organization 38

xc0+ xc1+ xc2+ xc3+ xc4= Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer  Repeat for BLOCKSIZE iterations  Send output buffer to DAC  Copy last N-1 samples to history pre-buffer SP HWI SP D/A HWI A/D T TO Technical Training Organization 39

Block FIR Filter Overview  Read block of data to input buffer  Convolve 1 st N samples with coefficients  Store result to 1 st location of output buffer  Repeat convolution advanced by 1 sample  Store result to 2 nd location of output buffer  Repeat for BLOCKSIZE iterations  Send output buffer to DAC  Copy last N-1 samples to history pre-buffer  Repeat above steps... SP HWI SP D/A HWI A/D xc0+ xc1+ xc2+ xc3+ xc4= 100 T TO Technical Training Organization 40

4 4 6 Double Buffer Management processBuffer FIR DataIn Get block of data 2.Start collecting next block while processing data 3.Prime for next block 4.Start collecting next block while processing data 5.Prime for next block  Make data buffers size of block plus history  Collect data in last ‘blocksize’ locations  After buffer is processed, copy last ‘history’ values to top of other buffer T TO Technical Training Organization 41

Interlaced Stereo Double Buffers 0 L1 R1 L2 R2... L8 R8 L9 R9 L10 R10 T TO Technical Training Organization L9 R9 L10 R10 L11 R11 L12 R12... L18 R18 L19 R19 L20 R20 #defineFIRSZ64 #defineHIST(2*FIRSZ-2) shortin[2][2*BUF+HIST]; shortout[2][2*BUF]; for ( i = 0; i < HIST; i++ ) pIn[i-HIST]= pPriorIn[i+2*BUF-HIST]; pPriorIn = pIn; fir(pIn-HIST, &coeffs[cSet][0], pOut, FIRSZ, BUF); fir(pIn+1-HIST, &coeffs[cSet][0], pOut+1, FIRSZ, BUF); Note: the driver will be passed the address where new data is to be collected. Only the SWI will be aware of the history segment that precedes it. 42

Lab 4: Software Interrupts - SWI  Create project using given SWI-based code  Build, download, and test on the EVM  Add QUEs to pass buffers between HWI and SWI  Build, load, test, note differences BIOS\Labs\Work HWI 4 swiProcBuf procBuf procBufs= QUE_get(&qProc); pIn = procBufs->pInBuf; for (i =0, i<HIST; i ++) pIn ][i]= pPriorIn ][ 2*BUF-HIST ]; if( sw0 == 1 ) FIR(in[ pIn-HIST ],out[ pOut ]) else {pOut[i]=pIn[i]} Audio Out (48 KHz) ADC AIC33 Audio In (48 KHz) McBSP DRR FIR.c FIR Code DAC AIC33 McBSP DXR mcbsp.c coeffs.c Coefficients BIOS\Labs\HW BIOS\Labs\Algos T TO Technical Training Organization isrAudio in[buf][i]=MCBSP1_DRR MCBSP1_DXR = out[buf][i]) if(bkCount==BKSZ) QUE_put(&qProc,intBufs); SWI_post(&swiProcBuf); 43

Lab 4a : procBuf() as a SWI 44 void procBuf ( short i;// loop index counter static short *pPriorIn=&in[1][0];// points to buf with hist data for ( i = 0; i < HIST; i++ ) // for all values in history, pIn[i-HIST]= pPriorIn[i+2*BUF-HIST]; // copy end old buf to top new pPriorIn = pIn; // cur.buf. is next 'old' buf if( sw0 == 1 ){// if SW0 down fir( pIn-HIST, &coeffs[sw1][0], pOut, FIRSZ, BUF );// FIR – L fir(pIn+1-HIST, &coeffs[sw1][0], pOut+1, FIRSZ, BUF );// FIR – R } else {// if SW0 is up, copy in to out for( i = 0; i < 2*BUF; i++ )// for all new L&R data, pOut[i] = pIn[i];// copy in buf to out buf } } void isrAudio (void){ static int dataIn, dataOut;// for read/write to McBSP CSL static short bkCnt = 0;// monitors # samples collected static short *pInBuf, *pOutBuf;// ptr to avail. in/out bufs static Bool N =0 ; if( bkCnt == 0 ) {// if there is no current buf pInBuf = &in[N][HIST]; // get in buf address pOutBuf = &out[N][0]; }// get out buf address dataIn = MCBSP1_DRR_32BIT;// get a stereo sample pInBuf[ bkCnt] = (short)dataIn;// add L sample to L block pInBuf[ bkCnt+1] = (short)(dataIn>>16);// R sample to R block dataOut = 0x0000FFFF & pOutBuf[bkCnt];// get L result dataOut |= 0xFFFF0000 & (pOutBuf[bkCnt+1]<<16);// append R result MCBSP1_DXR_32BIT = dataOut;// send stereo value to DAC bkCnt+=2; // inc.bk.ctr. by TWO samples if( bkCnt >= 2*BUF ) { pIn = &in[N][HIST]; // get in buf address pOut = &out[N][0]; // get out buf address N^=1; SWI_post(&swiProcBuf); // schedule SWI to process bufs bkCnt = 0; }// reset bk.ctr. for new buf's }

Lab 4b : Adding QUEues 45 void isrAudio (void){ static int dataIn, dataOut; // for read/write to McBSP CSL static short bkCnt = 0; // monitors # samples collected static short *pInBuf, *pOutBuf;// ptr to avail. in/out bufs static Msg intBufs; // ptr to struc of type MsgObj if( bkCnt == 0 ){ // if there is no current buf intBufs = QUE_get(&qDev); // get set of buf ptrs from Q pInBuf = intBufs->pInBuf; // get in buf address pOutBuf = intBufs->pOutBuf; }// get out buf address dataIn = MCBSP1_DRR_32BIT;// get a stereo sample pInBuf[ bkCnt] = (short)dataIn;// add L sample to L block pInBuf[ bkCnt+1] = (short)(dataIn>>16);// R sample to R block dataOut = 0x0000FFFF & pOutBuf[bkCnt];// get L result dataOut |= 0xFFFF0000 & (pOutBuf[bkCnt+1]<<16);// append R result MCBSP1_DXR_32BIT = dataOut;// send stereo value to DAC bkCnt+=2;// inc.bk.ctr. by TWO samples if( bkCnt >= 2*BUF ){// when the dbl block is full QUE_put(&qProc, intBufs); // get out buf address SWI_post(&swiProcBuf);// schedule SWI to process bufs bkCnt = 0; }// reset bk.ctr. for new buf's } void procBuf (){ short i; // loop index counter static short *pPriorIn=&in[1][0];// points to buf with hist data static Msg procBufs;// ptr to struc of type MsgObj procBufs = QUE_get(&qProc); // get a pair of bufs from HWI pIn = procBufs->pInBuf; // get in buf address pOut = procBufs->pOutBuf; // get out buf address for ( i = 0; i < HIST; i++ )// for all values in history, pIn[i-HIST]= pPriorIn[i+2*BUF-HIST];// copy end old buf to top new pPriorIn = pIn;// cur.buf. is next 'old' buf if( sw0 == 1 ) { // if SW0 down fir(pIn-HIST, &coeffs[sw1][0], pOut, FIRSZ, BUF);// FIR – L fir(pIn+1-HIST, &coeffs[sw1][0], pOut+1, FIRSZ, BUF); }// FIR - R else {// if SW0 is up, copy in to out for( i = 0; i < 2*BUF; i++ )// for all new L&R data, pOut[i] = pIn[i]; }// copy in buf to out buf QUE_put(&qDev, procBufs); // send bufs back to HWI }

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Lab Details FilterDebugRelease Off18%4.7% On61%6.5% HWI – based lab 3 FilterDebugRelease Off3.8%2.3% On45%3.7% SWI – based lab 4 Observations: Adding SWI dropped CPU load in all cases In addition, it greatly increases HWI response time, reduces interrupt latency, spreads instantaneous demand into average demand, lowering required processor speed greatly in most systems ! 47

HWI SWI 2 SWI 1 IDL time Highest Priority Lowest Priority Running Ready T TO Technical Training Organization Software Interrupts  MainHighlight  MainNormal 48