Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock VIA DOUBLING Applied VLSI Design – Final Presentation of Robert Gubitz

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock What is via doubling? design for manufacturability method to improve yield insertion of additional vias  pre-emptive technique to reduce impact of process variations and errors Slide 2

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Why via doubling? Slide 3 metal oxide damascene metallization (Cu) 2) metal deposition 3) metal CMP 1) etching of oxide trenches Via doubling prevents open, resistive and shortened Vias!

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Via Doubling in Cadance First Encounter via doubling = multiple cut vias can be inserted during NanoRoute Process use Route  NanoRoute  Mode and select DFM to get this dialog box Slide 4

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Design with and without doubled vias Only vias between transistor level and Metal layer 1 displayed for clear view! Slide 5

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Influence of via doubling on the design + makes design more resistant to parameter variability - increases chip area - increases wire length - increases capacitances - makes wiring more difficult w via doublingw/o via doubling % single cut vias5.9 %99.5 % % multi cut vias94.1 %0.5 % Total wire length 84,046 μm 79,183 μm Wire length on M1 252 μm 538 μm Wire length on M2 26,029 μm 25,195 μm Wire length on M3 34,345 μm 39,818 μm Wire length on M4 10,771 μm 6,971 μm Wire length on M5 12,648 μm 6,660 μm Slide 6

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Despite all disadvantages via doubling is used due to it‘s highly positive impact on yield! Slide 7

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock THANK YOU FOR YOUR ATTENTION