Readout of Temperature Monitor with SEABAS ’11 10/12 Y. Takubo (KEK) 1.

Slides:

Advertisements

Similar presentations

Embedded Systems I2CI2C. Feature 3 wire GND SCL(clock) SDA(data) All devices share the same bus wire Using wire and, each device gain access to bus (become.

Advertisements

1 Lab. 7 Signal Transmission between DSP and ADC/DAC  DAC/ADC/FGPA module:  With DAC/ADC, digital systems can be communicated with the analog world.

Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France 24 February 2003 News about SPECS system  SPECS system  SPECS-SLAVE chip  SPECS-SLAVE.

1 MICE Tracker Readout Update, Preparation for Cosmic Ray Tests Introduction/Overview AFE-IIt firmware development VLSB firmware development Hardware progress.

6 June 2002UK/HCAL common issues1 Paul Dauncey Imperial College Outline: UK commitments Trigger issues DAQ issues Readout electronics issues Many more.

Coordinate Based Tracking System

HT46 A/D Type MCU Series Data Memory (Byte) Program Memory HT46R22 (OTP) HT46C22 (Mask) 2Kx Kx16 4Kx HT46R23 (OTP) HT46C23 (Mask) HT46R24.

I2CI2C CS-423 Dick Steflik. Inter-Integrated Circuit Developed and patented by Philips for connecting low speed peripherals to a motherboard, embedded.

2 Lines Electronics I 2 C Analyzer Ching-Yen Beh Robert S. Stookey Advisor: Dr. J. W. Bruce.

Todd Moore for the DES CollaborationPS TalkJune 13 th, DES DHE CRATE SYSTEM MANAGEMENT & CONTROL Todd Moore University of Illinois, at Urbana-Champaign.

Arduino Nano to Uno I2C Communication Mike Pluma The-Bao Nguyen EE 444 Spring 2013.

Lecture 111 Lecture 11: Lab 3 Overview, the ADV7183B Video Decoder and the I 2 C Bus ECE 412: Microcomputer Laboratory.

Prototype Test of SPring-8 FADC Module Da-Shung Su Wen-Chen Chang 02/07/2002.

Lecture 20: Communications Lecturers: Professor John Devlin Mr Robert Ross.

EDA385 Project Presentation The Sound Disguiser. Overview Sample input audio Read input from the rotary encoder Process the audio due to choosen mode.

1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 3 Report Jack Hickish.

© Imperial College LondonPage 1 CERC Front End FPGA Development by Osman Zorba 12 May 2004 O. Zorba CALICE 12/05/2004.

I2C Master Core Simulation Environment. I2C Master Core Requirements Coverage (*) Requirement I2C IP RS-906: The I2C IP shall define the period of time,

Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.

Preliminary Design of FONT4 Digital ILC Feedback System Hamid Dabiri khah Queen Mary, University of London 30/05/2005.

Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.

Station Board Testing EVLA Correlator S/W F2F 3-4 April 2006 D. Fort.

Digital CFEB (an Update) B. Bylsma, EMU at CMS Week, March 16, Ben Bylsma The Ohio State University.

Adding SubtractingMultiplyingDividingMiscellaneous.

1Ben ConstanceFONT Meeting 1st August 2008 ATF2 digital feedback board 9 channel board with replaceable daughter board (RS232 etc.) − Board will log data.

AHCAL Physics Prototype. The Electronics Part Mathias Reinecke for the AHCAL developers DESY, March 2nd, 2010.

Methods to reduce dead time and achieve higher trigger rate. Sparsification Event blocking Parallel DAQ systems SFI Sequencing.

12 September 2006Silicon Strip Detector Readout Module J. Hoffmann SIDEREM SIlicon Strip DEtector REadout Module.

BMP085 Barometric Digital Pressure Sensor Module TYWu.

FEE Electronics progress PCB layout 18th March 2009.

3.13 How many output lines will a five-input decoder have?

Timer 1 and 2 operation, PWM Principles. Timer 1 Operation.

KEK visit to Fermilab --- Week 2 - Made Interface Bread Board to allow KEK system to switch the clock phase. After resolving grounding issues, every thing.

IBL – UniGe involvements UniGe Team : G. Barbier, F. Cadoux, A. Clark, S. Débieux, D. Ferrère, C. Husi, G. Iacobucci, M. Weber Other member (KEK): Y. Takubo.

Mircea Bogdan Chicago, Oct. 09, BIT, 500 MHz ADC Module for the KOTO Experiment The University of Chicago.

FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixture for software 9th June 2009.

Juin 1st 2010 Christophe Beigbeder PID meeting1 PID meeting Electronics Integration.

Tiltmeter, Compass,Temperature modules for the PPM.

October 12th 2005 ICALEPCS 2005D.Charlet The SPECS field bus  Global description  Module description Master Slave Mezzanine  Implementation  Link development.

Possible LLRF Configuration in ILC Sigit Basuki Wibowo LLRF Workshop, Shanghai - Nov 5, 2015.

Date of download: 6/23/2016 Copyright © 2016 SPIE. All rights reserved. Closed loop configuration of the resonant micro-optic gyros (RMOG). PM: phase modulator,

8255 Programmable Peripheral Interface

CALICE Readout Board Front End FPGA

14-BIT Custom ADC Board Rev. B

Iwaki System Readout Board User’s Guide

96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output

Chapter 11: Inter-Integrated Circuit (I2C) Interface

KRB proposal (Read Board of Kyiv group)

Basic PIC-C I2C Communication

I2C PROTOCOL SPECIFICATION

Communication Lines Fundamentals.

The Arduino Microcontroller: Atmel AVR Atmega 328

Torsten Alt, Kjetil Ullaland, Matthias Richter, Ketil Røed, Johan Alme

BJ Furman ME 106 Fundamentals of Mechatronics 15NOV2012

University of Illinois, at Urbana-Champaign

CALICE Readout Front End FPGA Development

EVLA MONITOR & CONTROL CDR

FEE Electronics progress

Tests Front-end card Status

Report on ATF2 Third Project Meeting ATF2 Magnet Movers ATF2 Q-BPM Electronics Is SLAC ILC Instrumentation Group a good name?

Adding with 9’s.

Adding with 10’s.

PID meeting Mechanical implementation Electronics architecture

TPC Electronics Meeting, 13/01/05 Carmen González Gutiérrez

Adding ____ + 10.

Fiber Optic Transciever Buffer

The QUIET ADC Implementation

Presentation transcript:

Readout of Temperature Monitor with SEABAS ’11 10/12 Y. Takubo (KEK) 1

Setup 2 AD7887 SMB SEABAS Module BCC board Two ADCs are mounted on SMB to read 16 temperature monitors. SDA and SCL are pulled up by FPGA on SEABAS.

Operation signals SDA SCL CONVB 3 We have no output from ADC.  We investigated the response more carefully.

Response from ADC SDA SCL CONVB Address byte: with write mode 4 This bit must be pulled down by the ADC. If you have any suggestions, please let me know.