A Fast SystemC Engine D. Gracia Pérez LRI, Paris South Univ. O. Temam LRI, Paris South Univ. G. Mouchard LRI, Paris South Univ. CEA

2 Introduction SystemC is becoming a de facto standard but: Too slow for cycle-accurate simulators SystemC performance decreased from version 1.0 to 2.0 SystemC implementation is not geared toward performance; more functionalities, less performance Little effort on SystemC scheduler; useless work is costly What do we need ? Compatibility with SystemC Support of features for cycle-accurate simulators (signals, modules) 1 - Better software implementation of SystemC core 2 - Better scheduling algorithm that limits useless work

3 SystemC Overview Simulators based on SystemC are structural: Hardware/software components  Modules Communications between modules  Ports / Signals Module behavior  Process Input Signal List  Sensitive List System time  Clocks sc_out sc_in Process sc_module sc_clock Sensitive list sc_signal sc_in_clk Process sc_module Steps by one delta cycle Processes Sensitive to clock edge Active signals list End of clock cycle when active signals list is empty SystemC Classes Dynamic Process Schedule SystemC dynamically wakes up a process whenever an input signal changes Sleeping Process Awaken Process

4 SC_METHOD Ports and signals Signal Propagation: Toggle buffer instead of Copy. 1 - Implementation of a New SystemC Engine Process sc_out<>::write() sc_port_b<>::operator  () virtual sc_signal<>::write() sc_prim_channel::request_update() sc_prim_channel_registry::request_update() Call Graph of Signal Writing Process Read BufferWrite Buffer Toggle BufferProcess reading signalProcess writing signal Avoid nested method calls of SystemC 2.0: inlining

5 2 - Improving SystemC Scheduling Performance is correlated with the number of process wakeups Extra information on signal dependency  Better scheduling S1 S3 S4 S5 S2 A BC D B C B Signal update Delta Cycle A D B C S1 S3 S4 S5 S2 A BC D BB Signal update Delta Cycle A D C Module Sleeping Process Signal Data Flow Dependency w/o dependency infowith dependency info AD BC 7 Wakeups5 Wakeups AD BC 2 Useless Wakeups Awaken Process Updated Signal

6 Acyclic Scheduling Add signal dependency information Build a signal dependency graph Assume that no true combinational cycle exists Find best (static) order of signals Schedule processes accordingly Fall-back for graph cycles: dynamic SystemC scheduling Better performance by compiling the schedule Signal Schedule S1S2 S3 S4 S5 A D Process Schedule Signal Update B C B S1 S3 S4 S5 S2 A BC D Module Process Signal Data Flow Dependency with dependency infoFinal Schedule

7 Implementing signal dependencies SC_CTOR(moduleB) { SC_METHOD(B); sensitive << inReq << inAck; outReq(inReq); outAck(inAck); } void B() { outReq = inReq; outAck = inAck; } Module B Source Code Combinational Processes I/O dependency B inAck outAck inReq outReq S5S3 S1 Extended syntax to specify dependencies Informations remains local to the module C outAck inReq inReady S4 S2 Module C Source Code SC_CTOR(moduleC) { SC_METHOD(C); sensitive << inReq << inReady; outAck(inReq); outAck(inReady); } void C() { outAck = inReq && inReady; } S5 B C

8 Experimental results Tested on two simulators : A 5-stage RISC processor simulator A superscalar processor simulator 10 million simulated instructions Pentium IV 2 Ghz From 1.96 to 3.56 speedup over SystemC Wakeups decreased by 29.9 % and 22.7 % Maximum # Delta Cycles decreases from 12 to 3 Wakeup distribution Performance # Wakeups

9 Conclusions FastSysC: Improved software implementation Improved scheduling algorithm Significant speedup on cycle-accurate simulators Compatible with any SystemC simulator using modules and signals Freely available at Future Work: Support for additional SystemC communication syntax (events, channels,…) Automatic generation of signal dependencies Part of a broad effort on simulation (MicroLib): Library of cycle-accurate processor simulators & processor component simulators Generic instruction-set simulators Fast simulation techniques

10 Q & A