QIE10 development Nov. 7, 2011: The first full-chip prototype was submitted to MOSIS. Output is 2-bit exponent (four ranges) and 6-bit mantissa (non-linear.

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Presentation transcript:

QIE10 development Nov. 7, 2011: The first full-chip prototype was submitted to MOSIS. Output is 2-bit exponent (four ranges) and 6-bit mantissa (non-linear ADC). LSB = 3fC, maximum input = 330 pC (approx. 17-bit dynamic range). 3 modes of operation: Normal, Program, and Charge Inject. Both inverting and non-inverting inputs are available. Separate Frontend (integration) and Backend (digital output) 40 MHz clock inputs. Parallel LVDS digital outputs (mantissa, exponent, CapID, timing discriminator). Programmable via shift register: - Timing discriminator threshold - Pedestal DAC - Separate CapID pedestals on the lowest range - Force to fixed range operation for testing - Charge injection DAC (8 levels, covering 2 points on each of the 4 ranges) - Input bias levels (allows adjusting input impedance, etc.) Two previous prototype submissions were for the input amp/splitter and ADC sections. Both functioned as expected, so success is expected for this first full-chip prototype.

QIE10 schematic Pad frame/ ESD protection Digital Output Sync Non-linear ADC (“6-bit”) 6-bit mantissa Digital bypass 4-phase analog and digital MUX Power-up reset Mode select (Normal, Program, or Charge Inject) Serial program shift register Clock buffers 4-phase ring counter 2-bit Exponent Range Select and MUX Inverting Input Non-inverting Input Charge Injection Input amps/splitters Programmable Input Bias Programmable CapID pedestals (lowest range) Bandgap reference Bias Timing discriminator Integrators 4 ranges, scaled by X8 Range0 Range1 Range2 Range3 2-bit CapID

LVDS outputs (6 bits mantissa, 2 bits exponent, 2 bits CapID) Non-inverting amp/splitter (negative current) Inverting amp/splitter (positive current) Digital LVDS Inputs (FEck, BEck, Reset) Inverting input bias Non-inverting input bias Digital power Mode control Serial program inSerial program out Analog power (5V, 3.3V) Timing discriminator LVDS out ADC Digital Bypass Integrators Timing Disc. Bandgap Ref. Bias Ring Input Bias Charge Inject Serial program shift register Range select