Chapter 8 Solving Larger Sequential Problems

8.1 Shift Registers A Simple 4-bit Shift Register Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers A Simple 4-bit Shift Register Shift registers are most commonly implemented with SR FF. JK FF could be used in place of the SR’s. D FF could also be used. Current output q is connected to next D FF input. At each clock, input x is shifted one place to the right.

8.1 Shift Registers A Simple 4-bit Shift Register Circuit Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers A Simple 4-bit Shift Register Circuit Timing Diagram P. 402

8.1 Shift Registers Leading-Edge Triggered Shift Register Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Leading-Edge Triggered Shift Register NOT gate is added at the clock input The Leading edge of the clock is the trailing edge of the flip-flop clock input. Clock input signal only goes to NOT gate. Circuit presents a load of 1 to the clock rather than a load of 4. P. 402

8.1 Shift Registers Shift Register with Load Reducing NOT gates Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Shift Register with Load Reducing NOT gates When a trailing-edge triggered shift register is desired, a second NOT gate is added. P. 402

8.1 Shift Registers Shift Register Storage Load = 0 : circular shift Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Shift Register Storage Load = 0 : circular shift Load = 1 : store x P. 403

8.1 Shift Registers Serial-in Serial-out Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Serial-in Serial-out Only 1 bit may be loaded into the register or read from the register at a time Large serial-in serial-out shift register is a memory similar to a disk. When Load = 0, data circulate around the n flip flops. When Load = 1, new value x is supplied . To initialize a 4-bit serial-in serial-out shift register to all 0’s, we would have to clock it four times with 0 on input x each time. To avoid this, most shift registers have an active low clear input.

8.1 Shift Registers Serial-in Parallel-out Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Serial-in Parallel-out 8-bit Serial-in Parallel-Out shift register using D ff (74164) P. 404

8.1 Shift Registers Parallel-in Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Parallel-in Require an input line for each flip flop. Static Load(74165) Load’ Enable Action 1(don’t load) 0(shift) CLR’ & PRE is high and Shift works 1 Don’t Work 0(load) X (Don’t care) Clock disable, IN2 load into the flip flop P. 404

8.1 Shift Registers Parallel-in Dynamic Load(74166) Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Parallel-in Dynamic Load(74166) Enable’ Load’ Action IN2 is stored in q2 1 q1 is shifted into q2 X (Don’t care) Nothing Change P. 404

8.1 Shift Registers Right/Left Shift Register Truth Table Circuit Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Right/Left Shift Register Truth Table Circuit Clear’ S0 S1 q1* q2* q3* q4* Static clear X Hole 1 q1 q2 q3 q4 Shift left LS Shift right RS Load IN1 IN2 IN3 IN4 P. 405

8.1 Shift Registers Example of Shift Register Problem Chapter 8 Solving Larger Sequential Problems 8.1 Shift Registers Example of Shift Register Problem Output z is 1 if input x has been alternating for 7 clock times Using 8-bit serial-in parallel-out shift register. P. 406

Chapter 8 Solving Larger Sequential Problems 8.2 Counters 74161 Counter Synchronous counting and loading and asynchronous clear. Load  = 0 : D = IND, C = INC B = INB A = INA Count (ENP=1, ENT=1) OV : Overflow P. 408

Chapter 8 Solving Larger Sequential Problems 8.2 Counters 74161 Counter Load  = 0 → x=1, y=1, z= INc  , w= INc, flip flop= INc Load  = 1 → x=0, w = z = 1, y = output of red AND gate y = 1 → J = K = 1 : flip flop change P. 408

Chapter 8 Solving Larger Sequential Problems 8.2 Counters 8-bit Counter Low-order counter is enable for the first 15 clocks. Low-order counter reaches 1111, OV signal enables the second counter. P. 408

8.2 Counters MOD-120 Counter(static clear) Use 74161 counter Chapter 8 Solving Larger Sequential Problems 8.2 Counters MOD-120 Counter(static clear) Use 74161 counter When reached maximum, count one more and clear the counter. 01111000(120) → clear the counter P. 409

8.2 Counters MOD-120 Counter(synchronous clear) Use 74163 counter Chapter 8 Solving Larger Sequential Problems 8.2 Counters MOD-120 Counter(synchronous clear) Use 74163 counter Detect 119(01110111) and reset it on the next clock pulse P. 409

8.2 Counters Down/Up’ Counter(1) Chapter 8 Solving Larger Sequential Problems 8.2 Counters Down/Up’ Counter(1) LD’ EN’ D/U’ O X Static load 1 Do nothing Clocked count up Clocked count down P. 410

8.2 Counters Down/Up’ Counter(2) Load’ = 0 → C = Inc (Preset or Clear) Chapter 8 Solving Larger Sequential Problems 8.2 Counters Down/Up’ Counter(2) Load’ = 0 → C = Inc (Preset or Clear) Load’ = 1, D/U’ = 1→ Clocked count down Load’ = 1, D/U’ = 0→ Clocked count up P. 410

8.2 Counters Asynchronous Binary Counter Chapter 8 Solving Larger Sequential Problems 8.2 Counters Asynchronous Binary Counter 7490 Base 10 2 x 5 7492 Base 12 2 x 6 7493 Base 16 2 x 8 7493 Asynchronous Binary Counter P. 410

8.2 Counters Clock Generator for every 9 input clock(1) Solution 1 Chapter 8 Solving Larger Sequential Problems 8.2 Counters Clock Generator for every 9 input clock(1) Solution 1 Use 74163(clocked clear) 0 1 2 3 4 5 6 7 8 0 1 2 … D is only 1 in state 8 → Clear Counter P. 412

8.2 Counters Clock Generator for every 9 input clock(2) Solution 2 Chapter 8 Solving Larger Sequential Problems 8.2 Counters Clock Generator for every 9 input clock(2) Solution 2 Use 74161(static clear) Count 9 before clearing counter State 9 remains for a short time P. 412 - 413

8.2 Counters Clock Generator for every 9 input clock(3) Solution 3 Chapter 8 Solving Larger Sequential Problems 8.2 Counters Clock Generator for every 9 input clock(3) Solution 3 Use 74163(synchronous load) 8 9 10 11 12 13 14 15 0 8 9 … Counter reaches 0, load 8 into counter P. 413

8.2 Counters Clock Generator for every 9 input clock(4) Solution 4 Chapter 8 Solving Larger Sequential Problems 8.2 Counters Clock Generator for every 9 input clock(4) Solution 4 Use 74163(Overflow) 7 8 9 10 11 12 13 14 15 7 8 9 … When counter is 15, load 7 into counter P. 414

8.3 Programmable Logic Devices(PLDs) Chapter 8 Solving Larger Sequential Problems 8.3 Programmable Logic Devices(PLDs) 16R4 PLD 16 : number of inputs to the and array 4 : number of flip flops P. 415

8.3 Programmable Logic Devices(PLDs) Chapter 8 Solving Larger Sequential Problems 8.3 Programmable Logic Devices(PLDs) Up/Down Counter using PLD Output F : counter is saturated Output G : counter is recycling State Table Equations DA = x’A’B + x’AB’ + x’yA + xAB + xy’A’B’ DB = x’yA + AB’ + x’B’ + y’B’ F = x’yAB + xyA’B’ G = x’y’AB + xy’A’B’ AB A*B* xy=00 xy=01 xy=10 xy=11 F G 0 0 0 1 1 1 1 0 P. 416

8.3 Programmable Logic Devices(PLDs) Chapter 8 Solving Larger Sequential Problems 8.3 Programmable Logic Devices(PLDs) Up/Down Counter using PLD P. 417

8.3 Programmable Logic Devices(PLDs) Chapter 8 Solving Larger Sequential Problems 8.3 Programmable Logic Devices(PLDs) PLDs Complex Programmable Logic Device(CPLD) Array of PLD-like blocks and programmable interconnection networks Field Programmable Logic Device(FPLD) For larger circuits Basic Building Block General purpose logic generator Multiplexer Flip flop These blocks are connected by a programmable routing networks.

8.3 Programmable Logic Devices(PLDs) Chapter 8 Solving Larger Sequential Problems 8.3 Programmable Logic Devices(PLDs) PLDs Field Programmable Logic Device(FPLD) Lookup Table(LUT) P. 418

8.3 Programmable Logic Devices(PLDs) Chapter 8 Solving Larger Sequential Problems 8.3 Programmable Logic Devices(PLDs) PLDs Field Programmable Logic Device(FPLD) Lookup Table(LUT) Example Cells are programmed ( 0 0 0 1 0 0 1 1) f = x’yz + xyz’ + xyz = yz + xy

8.3 Programmable Logic Devices(PLDs) Chapter 8 Solving Larger Sequential Problems 8.3 Programmable Logic Devices(PLDs) PLDs Field Programmable Logic Device(FPLD) f = x1x2’ + x2x3 P. 419

8.4 Design Using ASM Diagram Chapter 8 Solving Larger Sequential Problems 8.4 Design Using ASM Diagram Basic Blocks State Box Moore type output, one entry point, one exit point Decision Box Two way branch exit point, one entry point Mealy Output Box One entry point, one exit point Output when state transition takes place. P. 420

8.4 Design Using ASM Diagram Chapter 8 Solving Larger Sequential Problems 8.4 Design Using ASM Diagram Basic Blocks State A and input x = 1 System goes State B and output z State A and input x = 0 System goes State A P. 420

8.4 Design Using ASM Diagram Chapter 8 Solving Larger Sequential Problems 8.4 Design Using ASM Diagram Moore State Diagram z = 1 iff x has been 1 for 3 consecutive clock times P. 421

8.4 Design Using ASM Diagram Chapter 8 Solving Larger Sequential Problems 8.4 Design Using ASM Diagram Mealy State Diagram z = 1 iff x has been 1 for 3 consecutive clock times P. 422

8.4 Design Using ASM Diagram Chapter 8 Solving Larger Sequential Problems 8.4 Design Using ASM Diagram Serial Adder Controller 16 bit shift register Two operands are already loaded into registers P. 422

8.4 Design Using ASM Diagram Chapter 8 Solving Larger Sequential Problems 8.4 Design Using ASM Diagram Serial Adder Controller s : start the addition d : done Registers shifted right s = 1 : state 00 → 01 N = 111 : state 01 → 10 Next clock : state 10 → 00 P. 423

8.5 One Hot Encoding One Hot Encoding Design an ASM diagram Chapter 8 Solving Larger Sequential Problems 8.5 One Hot Encoding One Hot Encoding Design an ASM diagram Use one flip flop for each state That flip flop is 1 and all other are 0 Example with Figure 8.18 Four state → four flip flop(A,B,C,D) A* = x’(A + B + C + D) = x’ B* = xA C* = xB D* = x(C + D) z = D This approach is sometime used in designing large controllers.

8.6 Verilog for Sequential Systems Chapter 8 Solving Larger Sequential Problems 8.6 Verilog for Sequential Systems Structural Model of a D flip flop module D_ff ( q, clk, D, CLR); input clk, D, CLR; output q; reg q; always @ (negedge clk or negedge CLR) begin if (!CLR) q <= 0; else q <= D; end end module

8.6 Verilog for Sequential Systems Chapter 8 Solving Larger Sequential Problems 8.6 Verilog for Sequential Systems Shift Register using flip flop module module shift ( Q, x, clk, CLR); input x, clk, CLR; output [7:0]Q; wire [7:0]Q; D_ff Stage 7 (Q[7], x, clk, CLR); D_ff Stage 6 (Q[6], Q[7], clk, CLR); D_ff Stage 5 (Q[5], Q[6], clk, CLR); D_ff Stage 4 (Q[4], Q[5], clk, CLR); D_ff Stage 3 (Q[3], Q[4], clk, CLR); D_ff Stage 2 (Q[2], Q[3], clk, CLR); D_ff Stage 1 (Q[1], Q[2], clk, CLR); D_ff Stage 0 (Q[0], Q[1], clk, CLR); end module

8.6 Verilog for Sequential Systems Chapter 8 Solving Larger Sequential Problems 8.6 Verilog for Sequential Systems Single Module Shifter module shift ( Q, x, clk, CLR); input x, clk, CLR; output [7:0]Q; reg [7:0]Q; always (@ negedge clk) begin Q[0] <= Q[1]; Q[1] <= Q[2]; Q[2] <= Q[3]; Q[3] <= Q[4]; Q[4] <= Q[5]; Q[5] <= Q[6]; Q[6] <= Q[7]; Q[7] <= x; end module

8.7 More Complex Examples First Example Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples First Example The system keeps track of how many consecutive 1 inputs occur on input line x and then, starting at the first time that the input x is 0, it outputs on line z that same number of 1’s at consecutive clocks(z is 0 at all other time) Simple timing trace x 1 z P. 426

8.7 More Complex Examples First Example Solution 1 x = 1 → counts up Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples First Example Solution 1 x = 1 → counts up x = 0 → counts down, output 1 Max counting range : 14 P. 426

8.7 More Complex Examples First Example Solution 2 Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples First Example Solution 2 Max counting range : 15 Large number of 1’s Count 15 and output 1 P. 427

8.7 More Complex Examples First Example Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples First Example Solution 3(ignore inputs until 1 outputs are completed) x = 0 Q = 0 count = 0 EN = 0 z = 0 D/U = X x = 0 Q = 0 count = 1 EN = 1 z = 1 D/U = 1 x = 0 Q = 0 count > 1 EN = 1 z = 1 D/U = 1 Q <- 1 x = 1 Q = 0 count ≠ 15 EN = 1 z = 0 D/U = 0 x = 1 Q = 0 count = 15 EN = 0 z = 0 D/U = X x = X Q = 1 count > 1 EN = 1 z = 1 D/U = 1 x = X Q = 1 count = 1 EN = 1 z = 1 D/U = 1 Q <- 0

8.7 More Complex Examples First Example Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples First Example Solution 3(ignore inputs until 1 outputs are completed) J = x (D + C + B) K = D C B A z = Q + x Q (D + C + B + A) = Q + x (D + C + B + A) EN = x (A B C D) + z D/U = Q + x (D + C + B + A)

8.7 More Complex Examples First Example Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples First Example Solution 4 (using shift register) 12 bit shift register X = 1 → S0 = 1, S1 = 0, shift right, leftmost bit = 1 X = 0 → shift left, loading 0 from right P. 429

8.7 More Complex Examples Second Example Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples Second Example Count 16 state (1 2 4 7 11 0 6 13 5 14 8 3 15 12 10 9) State Table D C B A D* C* B* A* 1 P. 430

8.7 More Complex Examples Second Example Solution 1 (4 JK ff) Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples Second Example Solution 1 (4 JK ff) JD = CA + CB + BA, KD = C’B’ + C’A + B’A JC = D’A’ + D’B, KC = DA’ + D’BA JB = D’ + A’, KB = D + A’ JA = D’C + DC’, KA = D’B’ + CB’ + DC’B P. 430

8.7 More Complex Examples Second Example Solution 2 (Decoder Block) Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples Second Example Solution 2 (Decoder Block) Truth Table D C B A W X Y Z 1 P. 431

8.7 More Complex Examples Second Example Solution 2 (Decoder Block) Chapter 8 Solving Larger Sequential Problems 8.7 More Complex Examples Second Example Solution 2 (Decoder Block) W = CB’A + DB’A + CBA + DBA’ X = DB’ + D’B Y = C’A + CA’ Z = B’A’ + BA P. 431