1 Dynamic CMOS Chapter 9 of Textbook

2 Dynamic CMOS  In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. l fan-in of N requires 2N devices  Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. l requires only N + 2 transistors l takes a sequence of precharge and conditional evaluation phases to realize logic functions

3 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp CLK Out CLCL CLK A B C MpMp MeMe Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

4 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp CLK Out CLCL CLK A B C MpMp MeMe Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) on off 1 on !((A&B)|C)

5 Conditions on Output  Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.  Inputs to the gate can make at most one transition during evaluation.  Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

6 Properties of Dynamic Gates  Logic function is implemented by the PDN only l number of transistors is N + 2 (versus 2N for static complementary CMOS) l should be smaller in area than static complementary CMOS  Full swing outputs (V OL = GND and V OH = V DD )  Nonratioed - sizing of the devices is not important for proper functioning (only for performance)  Faster switching speeds l reduced load capacitance due to lower number of transistors per gate (C int ) so a reduced logical effort l reduced load capacitance due to smaller fan-out (C ext ) l no I sc, so all the current provided by PDN goes into discharging C L l Ignoring the influence of precharge time on the switching speed of the gate, t pLH = 0 but the presence of the evaluation transistor slows down the t pHL

7 Properties of Dynamic Gates, con’t  Power dissipation should be better l consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating l lower C L - both C int (since there are fewer transistors connected to the drain output) and C ext (since there the output load is one per connected gate, not two) l by construction can have at most one transition per cycle – no glitching  But power dissipation can be significantly higher due to l higher transition probabilities l extra load on CLK  PDN starts to work as soon as the input signals exceed V Tn, so set V M (switching threshold), V IH and V IL all equal to V Tn l low noise margin (NM L = V IL – V oL)  Needs a precharge clock

8 Dynamic Behavior CLK In 1 In 2 In 3 In 4 Out In & CLK Out Time, ns Voltage #TrnsV OH V OL VMVM NM H NM L t pHL t pLH t pre 62.5V0VV Tn 2.5-V Tn V Tn 110ps0ns83ps Evaluate Precharge

9 Gate Parameters are Time Independent  The amount by which the output voltage drops is a strong function of the input voltage and the available evaluation time. l Noise needed to corrupt the signal has to be larger if the evaluation time is short – i.e., the switching threshold is truly time independent. CLK V out (V G =0.55) V out (V G =0.5) V out (V G =0.45) V G is the input glitch

10 Power Consumption of Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp CLK Out CLCL Power only dissipated when previous Out = 0

11 Dynamic Power Consumption is Data Dependent ABOut Dynamic 2-input NOR Gate Assume signal probabilities P A=1 = 1/2 P B=1 = 1/2 Then transition probability P 0  1 = P out=0 x P out=1 = 3/4 x 1 = 3/4 Switching activity can be higher in dynamic gates! P 0  1 = P out=0 =3/4 static NOR gate P 0  1 = 3/16 = P out=0 x P out=1 =3/4 x ¼ = 3/16 Out precharge to 1, so P out=1 =1

12 Issues in Dynamic Design 1: Charge Leakage CLCL CLK Out A=0 MpMp MeMe Minimum clock rate of a few kHz Leakage sources CLK V Out Precharge Evaluate subthreshold conduction reverse bias diode

13 Impact of Charge Leakage  Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks l Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage. CLK Out

14 A Solution to Charge Leakage CLCL CLK MeMe MpMp A B !Out M kp Same approach as level restorer for pass transistor logic Keeper  Keeper compensates for the charge lost due to the pull- down leakage paths. Figure 9.33 on page 387

15 Issues in Dynamic Design 2: Charge Sharing CLCL CLK CaCa CbCb B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to static power consumption by downstream gates and possible circuit malfunction. When  V out = - V DD (C a / (C a + C L )) the drop in V out is large enough to be below the switching threshold of the gate it drives causing a malfunction.

16 Charge Sharing Example C y =50fF CLK AA B B BB CC y = A  B  C C a =15fFC c =15fFC b =15fFC d =10fF What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.) Load inverter a b dc

17 Charge Sharing Example What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.) C y =50fF CLK A!A B !B B C!C y = A  B  C C a =15fF C c =15fF C b =15fF C d =15fF Load inverter a b dc  V out = - V DD ((C a + C c )/((C a + C c ) + C y )) = - 2.5V*(30/(30+50)) = -0.94V. Load inverter should have switching threshold below 2.5 – 0.94 = 1.56V

18 Solution to Charge Redistribution CLK MeMe MpMp A B Out M kp CLK Precharge internal nodes using a clock- driven transistor (at the cost of increased area and power)

19 Issues in Dynamic Design 3: Backgate Coupling C L1 CLK B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 =0  Susceptible to crosstalk due to 1) high impedance of the output node and 2) capacitive coupling l Out2 capacitively couples with Out1 through the gate-source and gate-drain capacitances of M4 M1M1 M2M2 M3M3 M4M4 M5M5 M6M6

20 Backgate Coupling Effect Voltage Time, ns CLK In Out1 Out2  Capacitive coupling means Out1 drops significantly so Out2 doesn’t go all the way to ground Due to clock feedthrough

21 Issues in Dynamic Design 4: Clock Feedthrough CLCL CLK B A Out MpMp MeMe Coupling between Out and CLK input of the precharge device due to the gate- drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.  A special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node

22 Clock Feedthrough CLK In 1 In 2 In 3 In 4 Out In & CLK Out Time, ns Voltage Clock feedthrough

23 Cascading Dynamic Gates CLK Out1 In MpMp MeMe MpMp MeMe CLK Out2 V t CLKIn Out1 Out2 VV V Tn Only a single 0  1 transition allowed at the inputs during the evaluation period! Out2 should remain at VDD since Out1 transitions to 0 during evaluation a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. This loss will not be recovered and may result in reduced noise margin and potential malfunction. Setting all inputs to 0 during precharge The second dynamic inverter turns off (PDN) when Out1 reaches VTn

24 Domino Logic In 1 In 2 PDN In 3 MeMe MpMp CLK Out1 In 4 PDN In 5 MeMe MpMp CLK Out2 M kp 1  1 1  0 0  0 0  1 All inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1 a static inverter

25 Why Domino? In 1 CLK In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!

26 Domino Manchester Carry Chain C i,0 G0G0 CLK P0P0 P1P1 P2P2 P3P3 G1G1 G2G2 G3G3 C i,4

27 Domino Manchester Carry Chain C i,0 G0G0 CLK P0P0 P1P1 P2P2 P3P3 G1G1 G2G2 G3G3 C i, !(G 0 + P 0 C i,0 )!(G 1 + P 1 G 0 + P 1 P 0 C i,0 )

28 Domino Zero Detector CLK In 7 In 6 In 5 In 4 In 3 In 2 In 0 In 1 not zero

29 CLK A3 B3 A2 B2 A1 B1 A0 B0 Out Domino Comparator Out=1 if unequal

30 Properties of Domino Logic  Only non-inverting logic can be implemented, fixes include l can reorganize the logic using Boolean transformations l use differential logic (dual rail) l use np-CMOS (zipper) -Use nMOS logic gates and pMOS logic gates to perform operation  Very high speed l t pHL = 0 l static inverter can be optimized to match fan-out (separation of fan-in and fan-out capacitances)

31 Differential (Dual Rail) Domino A B MeMe MpMp CLK !Out = !(AB) !A!B M kp CLK Out = AB M kp MpMp Due to its high-performance, differential domino is very popular and is used in several commercial microprocessors! 1 0 on off

32 np-CMOS (Zipper) In 1 In 2 PDN In 3 MeMe MpMp CLK Out1 In 4 PUN In 5 MeMe MpMp !CLK Out2 (to PDN) 1  1 1  0 0  0 0  1 Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN to other PDN’s to other PUN’s

33 DCVS Logic In 1 In 2 PDN1 Out !In 1 !In 2 PDN2 !Out PDN1 and PDN2 are mutually exclusive 10 on off on Differential Cascade Voltage Switch Logic

34 DCVS Logic In 1 In 2 PDN1 Out !In 1 !In 2 PDN2 !Out PDN1 and PDN2 are mutually exclusive 10  0 on off  on on  off  on  off  1

35 DCVS Logic Example Out !Out B A!A B !B What is the logic ? xor xnor

36 How to Choose a Logic Style  Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing Style# TransEaseRatioed?DelayPower Comp Static81no31 CPL* no43 domino6 + 24no22 + clk DCVSL*103yes14 4-input NAND * Dual Rail  Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling. CPL: Complemantary Pass-transistor Logic