Digital Logic Design Lecture # 13 University of Tehran.

Slides:



Advertisements
Similar presentations
Random-Access Memory (RAM)
Advertisements

Combinational Circuits
Functions and Functional Blocks
Programmable Logic PAL, PLA.
Digital Logic Design Lecture # 17 University of Tehran.
FPGA structure and programming - Eli Kaminsky 1 FPGA structure and programming.
Parity. 2 Datasheets TTL:  CMOS: 
Chapter 6 – Selected Design Topics Part 4 – Programmable Implementation Technologies Logic and Computer Design Fundamentals.
Introduction to CMOS VLSI Design CAMs, ROMs, and PLAs
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR 1 Combinational Circuit – MSI Circuit ENCODER With the aid of K-map (don’t care situation), we can get D 0 =
Chapter 4 Gates and Circuits.
Registers  Flip-flops are available in a variety of configurations. A simple one with two independent D flip-flops with clear and preset signals is illustrated.

Multiplexers, Decoders, and Programmable Logic Devices
EE466:VLSI Design CAMs, ROMs, and PLAs. CMOS VLSI Design14: CAMs, ROMs, and PLAsSlide 2 Outline  Content-Addressable Memories  Read-Only Memories 
ECE 331 – Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #16) The slides included herein were taken.
Lecture 20: CAMs, ROMs, PLAs. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 20: CAMs, ROMs, and PLAs2 Outline  Content-Addressable Memories  Read-Only Memories.
ECE 301 – Digital Electronics
Digital Logic Design Lecture # 8 University of Tehran.
EE 261 – Introduction to Logic Circuits Module #8 Page 1 EE 261 – Introduction to Logic Circuits Module #8 – Programmable Logic & Memory Topics A.Programmable.
Khaled A. Al-Utaibi Memory Devices Khaled A. Al-Utaibi
Chapter 4 Gates and Circuits. 4–2 Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors.
Chapter 4 Gates and Circuits.
Memory and Programmable Logic
Digital Logic Design Lecture # 7 University of Tehran.
Random-Access Memory (RAM)
Memory and Programmable Logic Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush.
Logic Gates How Boolean logic is implemented. Transistors used as switches to implement Boolean logic: ANDOR Logic with Transistors.
Digital Logic Design Lecture # 3 University of Tehran.
Digital Logic. 4 Why is 32-bit or 64-bit significant in terms of speed, efficiency? 4 Difference between OR and XOR 4 What is a mux for? PLA 4 Two kinds.
Field-programmable logic devices FPLA circuits –Packaged PLA components with a fuse at every diode in both the AND and OR sections, that can be configured.
Memory and Programmable Logic Memory device: Device to which binary information is transferred for storage, and from which information is available for.
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /10/2013 Lecture 5: Combinational Logic Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE.
Digital Logic Structures MOS transistors logic gates functional units of a computer.
Digital Logic Design Lecture # 9 University of Tehran.
Digital Design: Principles and Practices
Digital Logic Design Lecture # 21 University of Tehran.
1 Memory Design EE 208 – Logic Design Chapter 7 Sohaib Majzoub.
Princess Sumaya University
Digital Logic Design Lecture # 2 University of Tehran.
Memory 10/27/081ECE Lecture. Memory Memory Types Using memory to implement logic functions 10/27/082ECE Lecture.
Digital Logic Design Lecture # 14 University of Tehran.
ITEC 352 Lecture 3 Low level components(2). Low-level components Review Electricity Transistors Gates Really simple circuit.
Outline MSI Parts as a Decoder Multiplexer Three State Buffer MSI Parts as a Multiplexer Realization of Switching Functions Using Multiplexers.
CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20.
CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Friday, February 14 CEC 220 Digital Circuit Design Slide 1 of 18.
CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers
IC design options PLD (programmable logic device)
Digital Logic Design Lecture # 15 University of Tehran.
Lecture # 5 University of Tehran
Programmable logic devices. CS Digital LogicProgrammable Logic Device2 Outline PLAs PALs ROMs.
Lecture # 10 University of Tehran
Programmable Logic Devices
Gunjeet Kaur Dronacharya Group of Institutions. Outline Introduction Random-Access Memory Memory Decoding Error Detection and Correction Programmable.
Chapter- 9 Programmable Logic Devices DHADUK ANKITA ENRL NO Noble Engineering College- Junagadh.
Memory and Programmable Logic
ETE Digital Electronics
Logic Devices. Decoder 2-to-4 Decoder 3-to-8 Decoder.
Computer Architecture & Operations I
Recap DRAM Read Cycle DRAM Write Cycle FAST Page Access Mode
Computer Architecture & Operations I
Electronics Technology
Dr. Clincy Professor of CS
How Boolean logic is implemented
ECE434a Advanced Digital Systems L02
13 Digital Logic Circuits.
Recall: ROM example Here are three functions, V2V1V0, implemented with an 8 x 3 ROM. Blue crosses (X) indicate connections between decoder outputs and.
ECE 352 Digital System Fundamentals
PROGRAMMABLE LOGIC DEVICES (PLD) UNIT-IV
Lecture 20: CAMs, ROMs, PLAs
Presentation transcript:

Digital Logic Design Lecture # 13 University of Tehran

Outline Rom

Rom Each of our design isn’t necessarily a function that can be realized with packages such as MUX’s, adders etc. Sometimes a function has to be realized from scratch using gates. To do this kind of design, and do the wiring, testing and reliability checks of a circuit like this can be time consuming and costly.

Rom (continued…) Consider a box like the one below and its truth table:

Rom (continued…) Building all the minterms we have:

Rom (continued…) To realize any function with four inputs, all we need is the 16 minterms shown in the last slide. The idea of a programmable device is actually to put such a structure in an IC, and let the user connect the minterms he/she needs to realize the particular function.

Rom (continued…) The structure shown in the previous slides for a programmable device is not practical nor efficient because of the large gates it is using. What we need to do here is to distribute these gates in our structure. For instance a distributed AND gate for a minterm would look like:

Rom (continued…) This NMOS structure with ratio logic is different from the CMOS logic we have seen so far. The shown structure can be redrawn as:

Rom (continued…) The OR gates of our structure can also be distributed through out. Combination of OR gates and AND gates to implement a function is shown in the following figure:

Rom (continued…) Now we are near to a real programmable device structure. What we need in a programmable device is the ability to realize any function we need. To have this we use ‘fusible logic’ in the OR plane of our structure, giving the use to diffuse any transistor, and thus reach any wanted design, whereas the AND plane that makes our minterms stays untouched.

Rom (continued…) From now on we will be using the following notation instead of the transistors notation using ‘.’s where connections are permanent and ‘x’s where they are programmed.

Rom (continued…) Consider the following structure. We can look at this structure as a memory component that gives us a specified content (output) for every address space (input) we ask for, but this memory can not be written to and is thus called a Read Only Memory (ROM). The ROMs we saw were structured as follows: AND plane  fixed OR plane  programmable

Rom (continued…) ROM structures have always been changing from when they started to form. After ROMs that were only programmed by the factory as asked for by the user came PROMs (Programmable ROMs). The user could program PROMs as he wished but only once and any mistake could not be undone. Then came EPROMs (Erasable Programmable ROMs) that could be erased using ultra violet light and were again programmed by the user through diffusing of unwanted transistors in the OR plane.

Rom (continued…) And last of all were the EEPROMs (Electrical Erasable Programmable ROMs) that no longer needed ultra violet light to be erased and could be erased in special voltage and timing conditions.