Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January 2008 1 ISIS1 Testbeam EUDET JRA1 Meeting, DESY 30 th January 2008 Scott Mandry LCFI Collaboration.

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Presentation transcript:

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January ISIS1 Testbeam EUDET JRA1 Meeting, DESY 30 th January 2008 Scott Mandry LCFI Collaboration University of Bristol

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Background Last autumn we held a three week testbeam at DESY; which started October 15 th. We tested prototype LCFI ISIS1 Sensors. This is to work towards using LCFI sensors in the EUDET beam telescope as a validation user. Around 6TB of data was taken. Analysis is ongoing. Today I will present the work preparing for this testbeam.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Introduction: The ISIS Sensor In-situ Storage Image Sensor, stores samples in ‘in-pixel’ CCD memory. Samples stored during bunch-crossings; charge only converted to voltage (& moved off-chip) in between bunch trains.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Introduction: The ISIS Sensor Prototype LCFI ‘Proof of Principle’ ISIS1 Sensor (produced by e2v). 16 x 16 pixel device, each 40µm x 160µm. Mechanical Alignment crucial & challenging.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Integrated Sensor Stack Precision Mechanical Support Structure. Thermally conductive pads couple heat through to external cooling stage. Operating Temperature is ~-20°C

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Electronics: Overview

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Testbeam 1

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Testbeam 2 VME Crate NI VMEBus Interface. 3 x CAEN V1724 ADC Cards. LCFI BVM2 Sequencer. Bristol Fanout Board.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Electronics: ISIS Carrier PCB Simple RAL Design, modified & produced by Bristol. Interfaces digital control signals with analogue bias voltages. CPLD provides ‘soft-wired’ routing of Sequencer control. CPLD also controls sensor row readout & column multiplexing. Central aperture to reduce Multiple Scattering.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Electronics: BVM2 Sequencer Base VME Module (v2) provides core of DAQ Hardware. Low cost modular Oxford/LCFI design. Dedicated clock circuitry distributes master clock through entire system. Sensor control sequence stored in RAM; CCD phases & readout synchronous with the master clock. User-definable 32-bit LVDS & TTL-LEMO interfaces allows for a highly flexible DAQ system. Spartan II FPGA implements rest of functionality, including VMEbus communications.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Electronics: Fanout Board Takes Sequencer control signals & ‘fans-out’ to/from array of sub-systems: TLU. ISIS Carrier PCBs. V1724 ADCs. CPLD keeps functionality flexible. Pin mappings firmware controlled. Allows debugging functionality. Allows DAQ topology to be changed during testbeam without hardware/firmware mods.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Electronics: Trigger Logic Unit Our good friend.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Firmware CPC (Column Parallel CCD) Sequencer Firmware (Rutherford Appleton Laboratory) ISIS Sequencer Firmware Ported CPC Firmware to ISIS. Developed VMEbus Block Transfer communications system. Added CAEN V1724 ADC control outputs. Incorporated triggered readout. Added DAQ_Busy registers: software run-time control of the readout hardware. ISIS Fanout Board Firmware Provides interface bridge between Sequencer and Multiple ISIS Carrier PCBs. Provides TLU interface. Added for debugging purposes a TLU Emulator (Trigger & Busy only). Allows optional system configuration: 1 plane / 5 planes. Use real / emulated TLU. Use triggered / untriggered readout.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Sensor Control Example of a single readout transaction: Uses Correlated Double Sampling. Column multiplexing interleaves data. Timing Diagram - Correlated Double Sampling Readout of pixel 1 from a row MUX Advance ADC Gate ADC Clock Phase 1 Phase 2 Phase 3 RG ISIS Output Four reset samples Four signal samples

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Sensor Control Readout Phase (screenshot from RAL sequence upload program):

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Sensor Control Complete Sequence with Integration Phase & Readout:

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Results 1 First Bristol ISIS1 Output 28 th June 2007 (Using RAL ISIS & PCB) (no DAQ at this stage) On-’Scope subtraction of pedestal from signal shows light detected. ISIS_output Delay Subtraction

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Software Labview Interface to CAEN V1724 ADCs: Provides ‘Peek and Poke’ access to control registers. Enables low-level characterization of ADCs, essential to building a DAQ Framework. ‘Practice-Run’ for building the full-scale Labview App.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Software Labview based Data Acquisition Software Controls the CAEN V1724 ADCs.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Testbeam 3 DAQ Software in operation.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Software (& Results 2) Segment of raw lab data, seen on Viewer Applet.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Results 3 Pre-Testbeam Results (Using Fe55 Source): X-rays detected, good to go.

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Results 4 Preliminary DESY Testbeam Results (6 GeV Electrons): Hit position correlations clearly visible: x(sensor) vs. x(sensor)y(sensor) vs. y(sensor)

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January Status Complete first generation Bristol Data Acquisition System for ISIS1 has been successfully developed. Preliminary results from first DESY testbeam look promising. Full testbeam analysis currently in-progress. Another testbeam is planned for this summer. ISIS1 will be easily integrated into a future EUDET testbeam. The ISIS principle has been shown to be a viable concept.