High Speed Pulse Generation Characterization Report By:Mironov Artiom Instructor: Yossi Hipsh.

Slides:



Advertisements
Similar presentations
I/O Organization popo.
Advertisements

Decoders/DeMUXs CS370 – Spring Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of.
FREQUENCY SHIFT KEYING
Stability of computer network for the set delay Jolanta Tańcula.
Transmission Basics ITNW 1325, Chapter III. OSI Physical Layer.
Multiplexing Multiplexing is the set of techniques that allows the simultaneous transmission of multiple signals across a single data link. A Multiplexer.
IERG 4100 Wireless Communications
Presentation Final Project name: Synchronization for Quantum Encryption System Project supervisor : Yossi Hipsh. Project performed by : Omer Mor, Oded.
Momentum Measurement Card Project supervised by: Mony Orbach Project performed by: Hadas Preminger, Uri Niv.
DIRECT MEMORY ACCESS CS 147 Thursday July 5,2001 SEEMA RAI.
1 Cross ID Tag identification emulator Performed by: Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion – Israel Institute of Technology.
Conversion Between Video Compression Protocols Performed by: Dmitry Sezganov, Vitaly Spector Instructor: Stas Lapchev, Artyom Borzin Cooperated with:
1 Pulse Generator High Speed Digital Systems Lab Semestrial project – Winter 2007/08 Final Presentation Instructor: Yossi Hipsh Students: Lior Shkolnitsky,
D0525 Project Receiver for Quantum Encryption System By: Dattner Yony & Sulkin Alex Supervisor: Yossi Hipsh High Speed Digital Systems Laboratory Spring.
Pulse Generator High Speed Digital Systems Lab Winter 2007/08 Design Presentation (Midterm ) Instructor: Yossi Hipsh Students: Lior Shkolnitsky, Yevgeniy.
1 Cross ID Tag identification emulator Part A final presentation Performed by: Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion –
D0525 Project Receiver for Quantum Encryption System By: Dattner Yony & Sulkin Alex Supervisor: Yossi Hipsh High Speed Digital Systems Laboratory Spring.
1 Cross ID tag emulator Performed by: Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion – Israel Institute of Technology Department.
Pulse Generator High Speed Digital Systems Lab Winter 2007/08 Project definition Instructor: Yossi Hipsh Students: Lior Shkolnitsky, Yevgeniy Lobanov.
Digital Voice Communication Link EE 413 – TEAM 2 April 21 st, 2005.
1 Cross ID Tag identification emulator Final presentation Performed by: Shuki Yasharzada Raanan Steinberg Yido Shalev Project instructor: Yossi Hipsh Technion.
High Speed Digital Systems Lab Spring/Winter 2010 Part A final presentation Instructor: Rolf Hilgendorf Students: Elad Mor, Ilya Zavolsky Integration of.
6/5/2008 High Speed Digital Systems Lab George Ghantous, Husam Khshaiboun 1 Cellular Activity Detection & Identification Final Presentation Supervised.
Quantum Encryption System - Synchronization presentation Midterm Project name: Synchronization for Quantum Encryption System Project supervisor : Yossi.
Testing elements in a fast communication channel 100GB/s Midterm Presentation Spring 2010 Developers: Hanna Alam and Yousef Badran Project supervised by:
Programmable Delay of Radar Pulse Technion-Israel Institute of Technology Electrical Engineering Department.
Spectrum Analyzer Ray Mathes, Nirav Patel,
RF Signal Wireless Test Lab Weekly Report 1: Objective: Familiarize all group members with RF wireless transmission capabilities and components.
Lab 04 :Serial Data Control Systems : Slide 2 Slide 3 Slide 4 NOR Gate: NAND Gate: NOR / NAND Alternate Symbols: Slide 5 XOR and XNOR Gate: Serial Data.
Sub-band Mixing and Addition of Digital Effects for Consumer Audio ELECTRICAL & ELECTRONIC ENGINEERING FINAL YEAR PROJECTS 2012/2013 Presented by Fionn.
Viking Pump Flow Manager - Phase 2 Senior Design May
Electronics Involves the use of devices and circuits to control the flow of electric current to achieve some purpose. These circuits contain: Resistors,
Data and Computer Communications Chapter 8 – Multiplexing
Wireless Sensor Monitoring Group Members: Daniel Eke (COMPE) Brian Reilly (ECE) Steven Shih (ECE) Sponsored by:
ISE. Tatjana Petrovic 249/982/22 ISE software tools ISE is Xilinx software design tools that concentrate on delivering you the most productivity available.
Reconfigurable Communication System Design
High Speed Digital Systems Lab Spring 2008 Students: Jenia Kuksin Alexander Milys Instructor: Yossi Hipsh Midterm Presentation Winter 2008/2009.
1 of 20 Z. Nikolova, V. Poulkov, G. Iliev, G. Stoyanov NARROWBAND INTERFERENCE CANCELLATION IN MULTIBAND OFDM SYSTEMS Dept. of Telecommunications Technical.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
Lessons Learned The Hard Way: FPGA  PCB Integration Challenges Dave Brady & Bruce Riggins.
Signal Encoding Techniques. Lecture Learning Outcomes Be able to understand, appreciate and differentiate the different signal encoding criteria available.
Chapter 10 Optical Communication Systems
1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.
LECC 2006, Valencia Potential Upgrade of the CMS Tracker Analog Readout Optical Links Using Bandwidth Efficient Digital Modulation Stefanos Dris Imperial.
Complementary Code Keying with PIC based microcontrollers for The Wireless Radio Communications.
White Space Internet Device By: Sean Iveson William Sadler.
Developing fast clock source with deterministic jitter Final review – Part A Yulia Okunev Supervisor -Yossi Hipsh HS-DSL Laboratory, Dept. of Electrical.
June 2005Computer Architecture, Background and MotivationSlide 1 Part I Background and Motivation.
Developing fast clock source with deterministic jitter Midterm review Yulia Okunev Supervisor -Yossi Hipsh HS-DSL Laboratory, Dept. of Electrical Engineering.
Signal: a supplementary material Taekyoung Kwon. signal A signal is a time-varying event that conveys information from a source to a destination (more.
Doppler Spread Estimation in Frequency Selective Rayleigh Channels for OFDM Systems Athanasios Doukas, Grigorios Kalivas University of Patras Department.
1 A High-Speed and Wide Detectable Frequency Range Phase Detector for DLLs Babazadeh, H.; Esmaili, A.; Hadidi, K.; NORCHIP, 2009 Digital Object Identifier:
Sub-Nyquist Reconstruction Characterization Presentation Winter 2010/2011 By: Yousef Badran Supervisors: Asaf Elron Ina Rivkin Technion Israel Institute.
P09311: FPGA Based Multi-Purpose Driver / Data Acquisition System Sponsor: Dr. Marcin Lukowiak Team MemberDisciplineRole Adam Van FleetEEProject Manager/Documentation.
1/8/ L16 Timing & Concurrency III Copyright Joanne DeGroat, ECE, OSU1 Timing & Concurrency III Delay Model foundations for simulation and.
Solid-State Devices & Circuits
Materials Flows Lay Out in Production Logistics
WP5 – Wirespeed Photonic Firewall Validation Start M27, finish M41(tbc) CIP now lead Description of Work –Establish test bed suitable to validated the.
8133A Overview. 8133A Overview 10-Feb04 Page A Overview 1) Specifications and Applications 2) Operational Overview 3) Block Diagram.
Performed by: Jenia Kuksin & Alexander Milys Instructor: Mr. Yossi Hipsh המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון -
Chapter 3 Boolean Algebra and Digital Logic T103: Computer architecture, logic and information processing.
Testing elements in a fast communication channel 100GB/s Final Presentation Spring 2010 Developers: Hanna Alam and Yousef Badran Project supervised by:
KRB proposal (Read Board of Kyiv group)
Design and Validation of a UWB Transmitter for FPGA Implementation
Advanced Wireless Networks
PIN DIODE.
WIRELESS ENERGY MEASUREMENT SYSTEM
Chapter 5: CPU Scheduling
Correlative level coding
Arithmetic Circuits.
Presentation transcript:

High Speed Pulse Generation Characterization Report By:Mironov Artiom Instructor: Yossi Hipsh

Overview The current project is a part of large research, being performed by EE Technion faculty. The research works on problems of wireless connections and implements new algorithm of blind receiving. The receiver has no information about carrier signal (phase, frequency), but using special signal, as LO, manages to retrieve the modulated info signal.

Overview Overview (cont.) Symbolical Block Scheme of receiver shown in Pic. 1.1 This special signal is periodic signal consisted of ones and zeros, for example as signal shown in Pic. 1.2 Our goal is to produce this fast I-O pulse function used, as LO at mixer and to implement it in the suggested receiver.

Project Milestones Learning of high-speed technologies and devices. Searching for an optimal, suitable solution. Exploration of alternative methods. Designing the whole pulse formation system. System verification at lower speed characteristics (5-10 GHz). Demonstration of possible system upgrade up to 20 GHz, within the current design with minor modifications.

Specifications High speed pulse signal up to 20 GHz operating frequency. Time pulse requirement The signal is periodic, consisted of 6-8 pulses.

Implementations High operating frequency of mixer. Digital Scope can be used as DSP component, due to its memory and large variety of math functions. Fast logical components. It is possible to use Pulsar system, as component in our system.

Proposed Solution Block Scheme, using pulsar to produce 20 GHz signal: In current solution we use Pulsar as initial signal generator. As it arises from experiments with Pulsar, it is able to produce pulses at 3 GHz frequency, that look like:

Proposed Solution Proposed Solution (cont.) As it can be seen signal produced by Pulsar is not sharp enough, beside the fact that it’s basic frequency is 3 GHz. So first we want to proceed the obtained signal from pulsar through buffer component, that makes signal look more like pulse. We want the resulting signal look like:

Proposed Solution Proposed Solution (cont.) Then we split the signal to two channels, while delaying one of them, thus we obtain 50 psec pulse, corresponding to 20 GHz frequency, as AND product. (Pic. 6) The delaying unit can be implemented by alteration of transmission line length.

Proposed Solution Proposed Solution (cont.) After splitting the signal to 6, we delay each one at needed interval, and then proceed them through OR gate, so we obtain: AND components can be optionally added at point 4, so we can control which pulse will be used in signal and which not:

Proposed Solution Proposed Solution (cont.) After exploring the components we discovered some, that meet the requirements. INPHI corporation provides logical components (OR, AND gates), splitters (fan-outs) and demultiplexers working at up to 50 GHz frequencies. Same components are also available at lower frequencies, such as 12.5 and 25 GHz. Hittite and On-Semi corporations also provide logical components and splitters at quite high frequencies, based on ECL and CML technologies. The available frequencies are at GHz range.

Gantt Chart Char-ion Report Making Purchase Semi Report Practical Work Finished Final Report