Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Transistor sizing: –Spice analysis. –Logical effort.

Slides:

Advertisements

Similar presentations

Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Advertisements

Logic Gate Delay Modeling -1 Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore

Topics Electrical properties of static combinational gates:

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Gate Design n Static complementary logic gate structures. n Switch logic. n Other.

Chapter 08 Designing High-Speed CMOS Logic Networks

Logical Effort A Method to Optimize Circuit Topology Swarthmore College E77 VLSI Design Adem Kader David Luong Mark Piper December 6, 2005.

A Look at Chapter 4: Circuit Characterization and Performance Estimation Knowing the source of delays in CMOS gates and being able to estimate them efficiently.

Logical Effort Section Problems: P6.2 Compute the oscillation frequency of a seven-stage ring oscillator using 0.18 micron technology. Does.

S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600S08) Lecture12: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering,

Modern VLSI Design: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Combinational logic functions n Static complementary logic gate structures.

Modern VLSI Design 2e: Chapter 4 Copyright  1998 Prentice Hall PTR Topics n Switch networks. n Combinational testing.

Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering, Brown.

Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harvey Mudd College Spring 2004.

Logical Effort.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 13 - More about.

Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Shifters. n Adders and ALUs.

1 MICROELETTRONICA Logical Effort and delay Lection 4.

Topics Combinational logic functions.

Introduction to CMOS VLSI Design Lecture 5: Logical Effort

Lecture 4 – Logical Effort

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Logical Effort - sizing for speed.

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 13: Logical Effort (2/2) Prof. Sherief Reda Division of Engineering, Brown.

Design and Implementation of VLSI Systems (EN0160)

EE 447 VLSI Design Lecture 5: Logical Effort. EE 447 VLSI Design 5: Logical Effort2 Outline Introduction Delay in a Logic Gate Multistage Logic Networks.

CMOS VLSI For Computer Engineering Lecture 4 – Logical Effort Prof. Luke Theogarajan parts adapted form Harris – and Rabaey-

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 5.1 EE4800 CMOS Digital IC Design & Analysis Lecture 5 Logic Effort Zhuo Feng.

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

1 Final Exam Review. 2 word7 is high if A2 A1 A0 = 111 word0 is high if A2 A1 A0 = 000 logical effort of each input is (1+3.5)/3 per wordline output.

Cascading CMOS gates. Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Goal l Designing for minimum propagation.

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 3 ASIC.

1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n Circuit design for FPGAs: –Logic elements. –Interconnect.

Review: CMOS Inverter: Dynamic

Elmore Delay, Logical Effort

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Switch networks. n Combinational testing.

Logical Effort: optimal CMOS device sizing Albert Chun (M.A.Sc. Candidate) Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE) Ottawa,

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Topics n Combinational logic functions. n Static complementary logic gate structures.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-1 Lectures 21, 22 FPGA and Top-Down Design Flow Mar. 3 and 5, 2003.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;

Introduction  Chip designers face a bewildering array of choices –What is the best circuit topology for a function? –How many stages of logic give least.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Combinational network delay. n Logic optimization.

Optimal digital circuit design Mohammad Sharifkhani.

Logical Effort and Transistor Sizing Digital designs are usually expected to operate at high frequencies, thus designers often have to choose the fastest.

Lecture 6: Logical Effort

Introduction to CMOS VLSI Design Lecture 5: Logical Effort GRECO-CIn-UFPE Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 6: Logical Effort

Linear Delay Model In general the propagation delay of a gate can be written as: d = f + p –p is the delay due to intrinsic capacitance. –f is the effort.

Topics Combinational network delay.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Circuit design for FPGAs n Static CMOS gate vs. LUT n LE output drivers n Interconnect.

EEC 118 Lecture #7: Designing with Logical Effort Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic.

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Topics n Power/ground routing. n Clock routing. n Floorplanning tips. n Off-chip.

FPGA-Based System Design: Chapter 2 Copyright  2004 Prentice Hall PTR Topics n Logic gate delay. n Logic gate power consumption. n Driving large loads.

Chapter 6 Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. High-Speed CMOS Logic Design.

Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Combinational network delay. n Logic optimization.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect.

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 A few notes for your design  Finger and multiplier in schematic design  Parametric analysis.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;

EE415 VLSI Design. Read 4.1, 4.2 COMBINATIONAL LOGIC.

CSE477 L11 Fast Logic.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 11: Designing for Speed Mary Jane Irwin (

COE 360 Principles of VLSI Design Delay. 2 Definitions.

Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

Lecture 6: Logical Effort

Lecture 6: Logical Effort

Introduction to CMOS VLSI Design Lecture 5: Logical Effort

Estimating Delays Would be nice to have a “back of the envelope” method for sizing gates for speed Logical Effort Book by Sutherland, Sproull, Harris Chapter.

Lecture 6: Logical Effort

COMBINATIONAL LOGIC - 2.

Presentation transcript:

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Transistor sizing: –Spice analysis. –Logical effort.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Transistor sizing n Not all gates need to have the same delay. n Not all inputs to a gate need to have the same delay. n Adjust transistor sizes to achieve desired delay.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example: adder carry chain + + aiai bibi aiai cici bibi cici bibi aiai bibi aiai c i+1 One stage: c i+1 =a i b i + (a i + b i ) c i c i+1

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Carry chain optimization n Connect four stages. n Optimize delay through carry chain by selecting transistor sizes.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Case 1 W/L for all stages: n = 0.75/0.5, p = 1.5/0.5

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Case 2 Wider pulldowns for first stage XOR, larger first stage inverter:

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Case 3 Larger transistors in second and third stages:

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Inter-stage effects in transistor sizing n Increasing a gate’s drive also increases the load to the previous stage: Larger drive Larger load

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort n Logical effort is a gate delay model that takes transistor sizes into account. n It is measured by the ratio of the input capacitance of a gate to the input capacitance of an inverter that delivers the same output current. (From Weste and Harris, p. 166, CMOS, VLSI Design.) n Allows us to optimize transistor sizes over combinational networks.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort gate delay model Gate delay is measured in units of minimum-size inverter delay . n Gate delay formula: –d = f + p. n Effort delay f is related to gate’s intrinsic work to compute its logic output. n Parasitic delay p depends on gate’s structure.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Effort delay n Effort delay has two components: –f = gh. n Electrical (fanout) effort h is determined by gate’s load: –h = C out /C in n Logical effort g is determined by gate’s function and structure.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort The logical effort values are derived from the n and p-transistor sizes of the gates, and are specified per each input. The denominator term, 3, comes from the sum of the channel widths of the n and p-transistor which is a measure of the gate capacitor (input capacitance). The numerator terms are the sums of the channel widths of the respective gates. For a more in depth discussion, please see

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort along a path n Logical effort along a chain of gates: –G =  g i. n Total electrical (fanout) effort along path depends on ratio of first and last stage capacitances: –H = C out /C in.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Branching effort n Takes into account fanout. n Branching effort at one stage: –b = (C onpath + C offpath / C onpath ) n Branching effort along path: –B =  b i.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Path delay n Path effort: –F = GBH. n Path delay is sum of delays of gates along the path: –D =  g i h i +  p i = D F + P.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Sizing the transistors n Optimal buffer chains are exponentially tapered: –f^ = F 1/N. n Determine W/L of each gate on path by working backward from the last gate: –C in,i = g i C out,i / f^

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example: logical effort n Size transistors in a chain of three two-input NAND gates. –First NAND is driven by minimum-size inverter. –Last NAND is connected to 4X inverter.

Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example, cont’d. n Logical effort G = 4/3 * 4/3 * 4/3. n Branching effort = 1. n Electrical effort = 4. n F = G B H = 9.5. n Optimum effort per stage f^ = 2.1. n Delay = 3*2.1 = 6.3