Static Logic vs. Pseudo-nMOS Static Logic includes pull-up and pull-down networks - 2n transistors for n-input function. Pseudo-nMOS - n+1 transistors.

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Presentation transcript:

Static Logic vs. Pseudo-nMOS Static Logic includes pull-up and pull-down networks - 2n transistors for n-input function. Pseudo-nMOS - n+1 transistors for n-input function Requires pull-up transistor be weaker than pull-down network (5:1) May eliminate p-transistors & possibly long pull-up chains Static power dissipation Pseudo-pMOS similar, except entirely out of p-transistors (good for NANDs) 93 weak

Building weak transistors Weakening transistors requires reducing width, increasing length (R=L/W) Create transistor with at least 5x greater resistance than others it fights against 94 R=10/3 R=2/3 R=2/15 R=10/3, less load on signal A AVdd

Like pseudo-nMOS except don't always pull up Initially charge output capacitance Need to make sure pull-down isn't fighting it Selectively discharge through pull-down network Avoids static power dissipation (and is faster), but more dynamic power Dynamic Logic 95 precharge

Redistribution of charge can degrade or change values Solution is to also precharge internal nodes Charge Sharing 96 precharge Note: Moves late-arriving signals closer to output Precharge A

Charge Leakage Compensate for leaking charge on output Advantages of dynamic logic (less transistors) but has static power dissipation Can avoid static power dissipation with inverter 97 weak precharge weak

Domino Logic Blocks in pseudo-nMOS style with inverter on output (non-inverting logic) Precharging all blocks - outputs equal to 0 Ensures no other pull-down networks are interfering with precharging When precharging is completed dominoes begin falling from first stage to last Final result is some output stay low while others go high 98 pull-down network precharge pull-down network precharge pull-down network precharge

Zipper Logic Alternating blocks of n-type and p-type networks (provides an inversion) By alternating stages, during precharge each gate's network is turned off by precharge of previous stage Similar to domino but transistors are easier to pack since there are equal numbers of each type on average 99 pull-down network precharge pull-up network pull-down network precharge

Static vs. Dynamic Logic Static + no charge sharing problems + no charge leakage problems + no static power dissipation - 2n transistors - series transistors always exist (slower) Dynamic + n+1 transistors - charge sharing - charge leakage - can have static power dissipation + potentially faster (eliminate series transistors) - more complex control (generate precharge signal) 100