SJTU Zhou Lingling1 Chapter 5 Differential and Multistage Amplifier

SJTU Zhou Lingling2 Outline Introduction The CMOS Differential Pair Small-Signal Operation of the MOS Differential Pair The BJT Differential Pair The differential Amplifier with Active Load Multistage Amplifiers

SJTU Zhou Lingling3 Introduction Two reasons of the differential amplifier suited for IC fabrication:  IC fabrication is capable of providing matched devices.  Utilizing more components than single-ended amplifier:  Differential circuits are much less sensitive to noise and interference.  Differential configuration enable us to bias the amplifier and to couple amplifier stages without the need for bypass and coupling capacitors.

SJTU Zhou Lingling4 The MOS Differential Pair Basic structure of differential pair. Characteristics

SJTU Zhou Lingling5 The MOS Differential Pair

SJTU Zhou Lingling6 Operation with a Common –Mode Input Voltage

SJTU Zhou Lingling7 Symmetry circuit. Common-mode voltage. Current I divides equally between two transistors. The difference between two drains is zero. The differential pair rejects the common- mode input signals. Operation with a Common –Mode Input Voltage

SJTU Zhou Lingling8 Operation with a Differential Input Voltage  The MOS differential pair with a differential input signal v id applied.  With v id positive: v GS1  v GS2, i D1  i D2, and v D1  v D2 ; thus ( v D2  v D1 ) will be positive.  With v id negative: v GS1  v GS2, i D1  i D2, and v D1  v D2 ; thus ( v D2  v D1 ) will be negative.

SJTU Zhou Lingling9 Differential input voltage. Response to the differential input signal. The current I can be steered from one transistor to the other by varying the differential input voltage in the range: When differential input voltage is very small, the differential output voltage is proportional to it, and the gain is high. Operation with a Differential Input Voltage

SJTU Zhou Lingling10 Large-Signal Operation  Transfer characteristic curves  Normalized plots of the currents in a MOSFET differential pair.  Note that V OV is the overdrive voltage at which Q 1 and Q 2 operate when conducting drain currents equal to I/2.

SJTU Zhou Lingling11 Large-Signal Operation Nonlinear curves. Maximum value of input differential voltage. When v id = 0, two drain currents are equal to I/2. Linear segment. Linearity can be increased by increasing overdrive voltage(see next slide). Price paid is a reduction in gain(current I is kept constant).

SJTU Zhou Lingling12 Large-Signal Operation The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of V OV.

SJTU Zhou Lingling13 Small-Signal Operation of MOS Differential Pair Linear amplifier Differential gain Common-mode gain Common-mode rejection ratio(CMRR)

SJTU Zhou Lingling14 Differential Gain  a common-mode voltage applied to set the dc bias voltage at the gates.  v id applied in a complementary (or balanced) manner.

SJTU Zhou Lingling15 Differential Gain Signal voltage at the joint source connection must be zero.

SJTU Zhou Lingling16 Differential Gain An alternative way of looking at the small- signal operation of the circuit.

SJTU Zhou Lingling17 Differential Gain Differential gain  Output taken single-ended  Output taken differentially  Advantages of output signal taken differentially Reject common-mode signal Increase in gain by a factor of 2(6dB)

SJTU Zhou Lingling18 Differential Gain MOS differential amplifier with r o and R SS taken into account.

SJTU Zhou Lingling19 Differential Gain  Equivalent circuit for determining the differential gain.  Each of the two halves of the differential amplifier circuit is a common-source amplifier, known as its differential “half-circuit.”

SJTU Zhou Lingling20 Differential Gain Differential gain  Output taken single-ended  Output taken differentially

SJTU Zhou Lingling21 Common-Mode Gain The MOS differential amplifier with a common- mode input signal v icm.

SJTU Zhou Lingling22 Common-Mode Gain  Equivalent circuit for determining the common-mode gain (with r o ignored).  Each half of the circuit is known as the “common-mode half-circuit.”

SJTU Zhou Lingling23 Common-Mode Gain Common-mode gain  Output taken single-ended  Output taken differentially

SJTU Zhou Lingling24 Common-Mode Rejection Ratio Common-mode rejection ratio(CMRR)  Output taken single-ended  Output taken differentially This is true only when the circuit is perfectly matched.

SJTU Zhou Lingling25 The BJT Differential Pair Basic operation Large-signal operation Small-signal operation  Differential gain  Common-mode gain  Common-mode rejection ration

SJTU Zhou Lingling26 The BJT Differential Pair The basic BJT differential-pair configuration.

SJTU Zhou Lingling27 Basic Operation  The differential pair with a common- mode input signal v CM.  Two transistors are matched.  Current source with infinite output resistance.  Current I divide equally between two transistors.  The difference in voltage between the two collector is zero.  The differential pair rejects the common-mode input signal as long as two transistors remain in active region.

SJTU Zhou Lingling28 Basic Operation  The differential pair with a “large” differential input signal.  Q 1 is on and Q 2 is off.  Current I entirely flows in Q 1.

SJTU Zhou Lingling29 Basic Operation  The differential pair with a large differential input signal of polarity opposite to that in (b).  Q 2 is on and Q 1 is off.  Current I entirely flows in Q 2.

SJTU Zhou Lingling30 Basic Operation  The differential pair with a small differential input signal v i.  Small signal operation or linear amplifier.  Assuming the bias current source I to be ideal and thus I remains constant with the change in v CM.  Increment in Q 1 and decrement in Q 2.

SJTU Zhou Lingling31 Large-Signal Operation

SJTU Zhou Lingling32 Large-Signal Operation Nonlinear curves. Linear segments. Maximum value of input differential voltages Enlarge the linear segment by including equal resistance R e in series with the emitters.

SJTU Zhou Lingling33 Large-Signal Operation The transfer characteristics of the BJT differential pair (a) can be linearized by including resistances in the emitters.

SJTU Zhou Lingling34 Small Signal Operation The currents and voltages in the differential amplifier when a small differential input signal v id is applied.

SJTU Zhou Lingling35 Small Signal Operation A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal v id ; dc quantities are not shown.

SJTU Zhou Lingling36 Small Signal Operation  A differential amplifier with emitter resistances.  Only signal quantities are shown (in color).

SJTU Zhou Lingling37 Input Differential Resistance Input differential resistance is finite. The resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by (1+β). Input differential resistance of differential pair with emitter resistors.

SJTU Zhou Lingling38 Differential Voltage Gain Differential voltage gain  Output voltage taken single-ended  Output voltage taken differentially

SJTU Zhou Lingling39 Differential Voltage Gain Differential voltage gain of the differential pair with resistances in the emitter leads  Output voltage taken single-ended  Output voltage taken differentially The voltage gain is equal to the ratio of the total resistance in the collector circuit to the total resistance in the emitter circuit.

SJTU Zhou Lingling40 Differential Half-Circuit Analysis  Differential input signals.  Single voltage at joint emitters is zero.  The circuit is symmetric.  Equivalent common-emitter amplifiers in (b).

SJTU Zhou Lingling41 Differential Half-Circuit Analysis  This equivalence applies only for differential input signals.  Either of the two common- emitter amplifiers can be used to find the differential gain, differential input resistance, frequency response, and so on, of the differential amplifier.  Half circuit is biased at I/2.  The voltage gain(with the output taken differentially) is equal to the voltage of half circuit.

SJTU Zhou Lingling42 Differential Half-Circuit Analysis  The differential amplifier fed in a single-ended fashion.  Signal voltage at the emitter is not zero.  Almost identical to the symmetric one.

SJTU Zhou Lingling43 Common-Mode Gain The differential amplifier fed by a common-mode voltage signal v icm.

SJTU Zhou Lingling44 Common-Mode Gain Equivalent “half-circuits” for common-mode calculations.

SJTU Zhou Lingling45 Common-Mode Gain Common-mode voltage gain  Output voltage taken single-ended  Output voltage taken differentially

SJTU Zhou Lingling46 Common-Mode Rejection Ratio Common-mode rejection ratio  Output voltage taken single-ended  Output voltage taken differentially This is true only when the circuit is symmetric. Mismatch on CMRR

SJTU Zhou Lingling47 Input Common-Mode Resistance  Definition of the input common-mode resistance R icm.  The equivalent common-mode half-circuit.

SJTU Zhou Lingling48 Input Common-Mode Resistance Input common-mode resistance Input common-mode resistance is very large.

SJTU Zhou Lingling49 The Differential Amplifier with Active Load Replace resistance R D with a constant current source results in a much high voltage gain as well as saving in chip area. Convert the output from differential to single-ended.

SJTU Zhou Lingling50 The Active-Loaded MOS Differential Pair The active-loaded MOS differential pair.

SJTU Zhou Lingling51 The Active-Loaded MOS Differential Pair The circuit at equilibrium assuming perfect matching.

SJTU Zhou Lingling52 The Active-Loaded MOS Differential Pair The circuit with a differential input signal applied, neglecting the r o of all transistors.

SJTU Zhou Lingling53 The Bipolar Differential Pair with Active Load Active-loaded bipolar differential pair.

SJTU Zhou Lingling54 Multistage Amplifier A four-stage bipolar op amplifier A two-stage CMOS op amplifier

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SJTU Zhou Lingling56 Multistage Amplifier The first stage(input stage) is differential-in, differential-out and consists of Q 1 and Q 2. The second stage is differential-in, single-ended-out amplifier which consists of Q 3 and Q 4. The third stage is CE amplifier which consists of pnp transistor Q 7 to shifting the dc level. The last stage is the emitter follower. Biasing stage.

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SJTU Zhou Lingling58 Multistage Amplifier Equivalent circuit for calculating the gain of the input stage of the example. Input differential resistance Gain of first stage

SJTU Zhou Lingling59 Multistage Amplifier Equivalent circuit for calculating the gain of the second stage of the example. Gain of second stage

SJTU Zhou Lingling60 Multistage Amplifier Equivalent circuit for calculating the gain of the third stage of the example. Gain of third stage

SJTU Zhou Lingling61 Multistage Amplifier Equivalent circuit for calculating the gain of the output stage of the example. Gain of output stage Output resistance