DMA Driver APIs DMA State Diagram Loading Driver and Opening Channel DMA Channel Attributes Loading Data to a Channel Unloading Data from a Channel.

Slides:



Advertisements
Similar presentations
CPU Structure and Function
Advertisements

Device Drivers. Linux Device Drivers Linux supports three types of hardware device: character, block and network –character devices: R/W without buffering.
R4 Dynamically loading processes. Overview R4 is closely related to R3, much of what you have written for R3 applies to R4 In R3, we executed procedures.
Module R2 Overview. Process queues As processes enter the system and transition from state to state, they are stored queues. There may be many different.
Memory management.
Direct Memory Access Introduction to 8237
1 Homework Reading –Review previous material on “interrupts” Machine Projects –MP4 Due today –Starting on MP5 (Due at start of Class 28) Labs –Continue.
Interfacing. This Week In DIG II  Basic communications terminology  Communications protocols  Microprocessor interfacing: I/O addressing  Port and.
DIRECT MEMORY ACCESS CS 147 Thursday July 5,2001 SEEMA RAI.
Network Adapter Driver NCTU High Speed Network Lab.
The hardware ringbuffer Understanding the RTL-8139 mechanism for packet reception.
Unit-5 CO-MPI autonomous
Group 7 Jhonathan Briceño Reginal Etienne Christian Kruger Felix Martinez Dane Minott Immer S Rivera Ander Sahonero.
1-1 NET+OS Software Group Serial EEPROM API Supported Serial EEPROM parts Serial EEPROM API introduction Detailed Serial EEPROM API Function presentation.
Multicore Navigator: Queue Manager Subsystem (QMSS)
POSIX: Files Introduction to Operating Systems: Discussion 1 Read Solaris System Interface Guide: Ch. 5.1 Basic File I/O.
The DMA Controller Definition and Advantages Hardware Modes Port A Special Function.
FINAL MPX DELIVERABLE Due when you schedule your interview and presentation.
1-1 Embedded Network Interface (ENI) API Concepts Shared RAM vs. FIFO modes ENI API’s.
ENEE 440 Chapter DMA Controller 8237 DMA Controller Summary Direct Memory Access means that the microprocessor is not involved in the transfer.
1-1 NET+OS Software Group Flash API Multiple flash memory bank support New Flash API introduction Detailed Flash API Function presentation Supporting.
CS 450 Module R5. Next Week Reminder: R3 & R4 is due next Friday. No documentation due. You do not need to turn in a copy of your source code. Remember.
EE 445S Real-Time Digital Signal Processing Lab Fall 2011 Lab #2 Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6713 DSP.
Ethernet Driver Changes for NET+OS V5.1. Design Changes Resides in bsp\devices\ethernet directory. Source code broken into more C files. Native driver.
Using Direct Memory Access to Improve Performance
Device Drivers CPU I/O Interface Device Driver DEVICECONTROL OPERATIONSDATA TRANSFER OPERATIONS Disk Seek to Sector, Track, Cyl. Seek Home Position.
KeyStone Training Multicore Navigator: Packet DMA (PKTDMA)
Renesas Technology America, Inc. Flash!. CPU Rewrite CPU-rewrite is a term that refers to an Renesas MCU’s ability to erase/program its own internal Flash.
Queues, Pipes and Sockets. QUEUE A structure with a series of data elements with the first element waiting for an operation Used when an element is not.
1 DSP handling of Video sources and Etherenet data flow Supervisor: Moni Orbach Students: Reuven Yogev Raviv Zehurai Technion – Israel Institute of Technology.
CSNB374: Microprocessor Systems Chapter 5: Procedures and Interrupts.
Input-Output Organization
© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Module Introduction Purpose  This training module provides an overview of the peripherals.
Module R3 Process Scheduling. Module R3 involves the creation of a simple “Round Robin” dispatcher. The successful completion of this module will require.
Unit - 2 DMA 8237A-5.
Stan Smith Intel SSG/DPD February, 2015 Kernel OpenFabrics Interface Initialization.
Embedded Network Interface (ENI). What is ENI? Embedded Network Interface Originally called DPO (Digital Product Option) card Printer without network.
1 ARM University Program Copyright © ARM Ltd 2013 Using Direct Memory Access to Improve Performance.
The computer system’s I/O architecture is its interface to the outside world. This architecture provides a systematic means of controlling interaction.
80386DX functional Block Diagram PIN Description Register set Flags Physical address space Data types.
12/16/  List the elements of 8255A Programmable Peripheral Interface (PPI)  Explain its various operating modes  Develop a simple program to.
COLONYWIRELESS September 26, Outline 1.Motivation and Goals 2.Introduction to the XBee 3.The Wireless Library 4.Example Packet Group 5.The Token.
Using Multicore Navigator CIV Application Team January 2012.
How to write a MSGQ Transport (MQT) Overview Nov 29, 2005 Todd Mullanix.
UDI Advanced Topics DMA and Interrupts Robert Lipe UDI Development Team Lead
Sairajiv Burugapalli. This chapter covers three main categories of classic software vulnerability: Buffer overflows Integer vulnerabilities Format string.
Interrupt driven I/O Computer Organization and Assembly Language: Module 12.
Direct Memory Access (DMA). DMA Features  7 independently configurable channels  Software programmable priorities: Very high, High, Medium or Low. 
Direct Memory Access Sequence of events:  A device (peripheral, CPU) requests a controller to transfer information;  The controller request control over.
Internal Programming Architecture or Model
UDI Network Drivers Network Interface Metalanguage Barry Feild SCO Server Products Group
WINLAB Open Cognitive Radio Platform Architecture v1.0 WINLAB – Rutgers University Date : July 27th 2009 Authors : Prasanthi Maddala,
EE 345S Real-Time Digital Signal Processing Lab Fall 2008 Lab #3 Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6713 DSP.
Homework Reading Machine Projects
Microprocessor and Assembly Language
Direct Memory address and 8237 dma controller LECTURE 6
Homework Reading Machine Projects Labs
EE 445S Real-Time Digital Signal Processing Lab Spring 2017
NS Training Hardware.
DMA CONTROLLER WHOLE WORKING
Chapter 13 DMA Programming.
EE 445S Real-Time Digital Signal Processing Lab Fall 2013
CPE 323 Introduction to Embedded Computer Systems: DMA Controller
Code Review for IPv4 Metarouter Header Format
Code Review for IPv4 Metarouter Header Format
Moving Arrays -- 2 Completion of ideas needed for a general and complete program Final concepts needed for Final DMA.
Moving Arrays -- 2 Completion of ideas needed for a general and complete program Final concepts needed for Final DMA.
NS Training Hardware.
NS Training Hardware.
Presentation transcript:

DMA Driver APIs DMA State Diagram Loading Driver and Opening Channel DMA Channel Attributes Loading Data to a Channel Unloading Data from a Channel

DMA Driver State Diagram Idle Enabled Disabled dmaLoadDriver() dmaOpenChannel() dmaDisableChannel() dmaEnableChannel() dmaCloseChannel() dmaLoadChannel() dmaUnloadChannel()

Loading DMA Driver prototype: int dmaLoadDriver(void) Returns 0 always.

Opening a DMA Channel prototype: int dmaOpenChannel( int *channel_ID, int channel_type, unsigned int option_flags, int ring_size, dmaReleaseType release_rtn) example: rc = dmaOpenChannel ( &channel_id, DMA_FIFO_1_TX, (DMA_MEM_TO_MEM_MODE | DMA_DADDR_INCR | DMA_SADDR_INCR), 64, releaseFunction); Returns Error Code

dmaOpenChannel Return Codes Possible Return Values for dmaOpenChannel() DMA_SUCCESS DMA_DRIVER_UNLOADED DMA_INVALID_FLAG DMA_CHANNEL_INUSE DMA_INVALID_RING_SIZE DMA_CALLBACK_UNDEFINED MA_INVALID_STATE DMA_SYSTEM_ERROR DMA_CHANNEL_UNSUPPORTED

Channel ID prototype: int dmaOpenChannel( int *channel_ID, int channel_type, unsigned int option_flags, int ring_size, dmaReleaseType (release_rtn) Handle for opened channel, used in various DMA APIs.

Channel Type prototype: int dmaOpenChannel( int *channel_ID, int channel_type, unsigned int option_flags, int ring_size, dmaReleaseType release_rtn) Peripheral FIFO DMA Memory “Fly-By Write” Peripheral FIFO DMA Memory “Fly-By Read” DMA_FIFO_1_TX (Channel 4) DMA_FIFO_1_RX (Channel 3)

Option Flags DMA Operation Mode –DMA_MEM_TO_MEM Burst Transfer Size –DMA_8_BYTE_BURST –DMA_16_BYTE_BURST Channel Request Source –DMA_EXTERNAL_REQ Source Address Increment –DMA_SRC_INCR Destination Address Increment –DMA_DADDR_INC DMA Transaction Operand Size –DMA_8_BIT –DMA_16_BIT These Flags Configure the DMA Channel Control Registers prototype: int dmaOpenChannel( int *channel_ID, int channel_type, unsigned int option_flags, int ring_size, dmaReleaseType release_rtn)

option_flags: DMA_Operation Mode Peripheral FIFO Memory Peripheral FIFO Memory Default Setting “Fly-By” Memory DMA Memory DMA_MEM_TO_MEM DMA OR

option_flags : Burst Transfer Size BCLK TA* Default Setting DMA_8_BYTE_BURST DMA_16_BYTE_BURST 1 Long Word (4 Bytes) 2 Long Words (8 Bytes) 4 Long Words (16 Bytes)

option_flags : Channel Request Source Net+ARM DREQ* DACK* DONE* Peripheral DMA_EXTERNAL_REQ Net+ARM DREQ* DACK* DONE* Peripheral Default Setting Internal Fly-By peripheral* OR Mem-to-Mem under software control *Note: Internal Fly-By hardwired to ENI RX and ENI TX

option_flags : Address Increment Applies to Memory-to-Memory DMA only. Source Memory Destination Memory Source Range Destination Range DMA_DADDR_INC DMA_SRC_INCR Source Memory Destination Memory Destination Range DMA_DADDR_INC Default Setting Source Location *Note: It never makes sense to NOT increment the destination address DMA

option_flags : DMA Transaction Operand Size 8-bit Peripheral FIFO Memory 16-bit Peripheral FIFO Memory DMA_8_BIT DMA_16_BIT 32-bit Peripheral FIFO Memory Default Setting DMA

DMA Channel Ring Size prototype: int dmaOpenChannel( int *channel_ID, int channel_type, unsigned int option_flags, int ring_size, dmaReleaseType release_rtn) Ring Size = Number of Buffer Descriptors: Max 64 for Mem-to-Mem Max 128 for Fly-By

DMA Channel ring_size DMA Channel Buffer Descriptor Pointer System Memory Buffer Descriptor Ring Area (CONTIGUOUS) dmaOpenChannel() allocates BD ring area from heap, based on int ring_size.

Release Callback prototype: void (*dmaReleaseType) (int channel_ID, dmaMessageType *request_msg) Enabled dmaLoadChannel() The defined callback will be called when the dmaLoadChannel() request has completed, with input parameters channel_ID and *request_msg. prototype: int dmaOpenChannel( int *channel_ID, int channel_type, unsigned int option_flags, int ring_size, dmaReleaseType release_rtn)

Loading a Channel Loading a channel configures the previously allocated Buffer Descriptors. prototype: int dmaLoadChannel( int channel_ID, dmaMessageType request_msg) typedef struct dmaMessageStruct { struct dmaMessageStruct*next; void*src_addr; void*dst_addr; longlength; longstatus; longerror_value; longreserved[4]; } dmaMessageType;

Fly-By Read Loading Memory Destination Area Peripheral FIFO Set up enough dmaMessageType’s to accommodate all expected data. *next  Address of next dmaMessageType if more than 32Kbytes needed. *src_addr  Not Used *dst_addr  Start of Destination (incrementing) length  Up to 32Kbytes

Fly-By Write Loading Memory Source Data Area Peripheral FIFO Set up enough dmaMessageType’s to accommodate outgoing data. *next  Address of next dmaMessageType if more than 32Kbytes needed. *src_addr  Start of Data Buffer (incrementing) *dst_addr  Not Used length  Up to 32Kbytes

Memory to Memory Loading Memory Source Data Area Memory Set up enough dmaMessageType’s to accommodate outgoing data. *next  Address of next dmaMessageType if more than 32Kbytes needed. *src_addr  Start of Source Data Buffer (incrementing) *dst_addr  Start of Destination Buffer (incrementing) length  Up to 32Kbytes Destination

UnLoading a Channel UnLoading a channel is called to remove a processed request from the DMA’s queue when no release callback is supplied. prototype: int dmaUnloadChannel( int channel_ID, dmaMessageType *request_msg, int wait_time) DMA Channel Buffer Descriptor Pointer System Memory Buffer Descriptors Used Unused Used Unused Unload Note: Each request_msg uses one buffer descriptor.

Request Processing - no Release Callback dmaLoadChannel() DMA Channel Request Queue DMA ISR DMA Channel Release Queue* dmaUnloadChannel() * Not built when a release callback is provided fills emptied by fills emptied by

DMA API SUmmary Load the driver - dmaLoadDriver Open a channel - dmaOpenChannel –Set channel ID, type, options, buffer ring size, release callback Load the channel –Flyby – source or destination address –Memory to memory – both source and dest Unload the channel if no release callback supplied