1 Agenda 11:00 - Introduction (Damoulakis) 11:05 - Overview of Test Needs (Ken LaBel) Low Cost Test Needs High Speed Test Needs 11:15 - Team Responsibilities.

Slides:

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Presentation transcript:

1 Agenda 11:00 - Introduction (Damoulakis) 11:05 - Overview of Test Needs (Ken LaBel) Low Cost Test Needs High Speed Test Needs 11:15 - Team Responsibilities & Partnerships (Jim Howard) Managerial Topics - Team, Responsibilities, Partnerships Testing - How & Why Functional/Facilities/Usage DUT Independence Design Flows 11:35 - Low Cost/Speed Tester (Hak Kim) Design Overview 11:45 - High Speed Tester (Scott Stansberry) Requirements Design Overview Status 12:00 – Lunch (provided) 12:30 - User I/F & VHDL Modules (Charlie) 12:50 - Test Coupons (Valencia Joyner) Describe coupon designs & Tests Describe SEU design & Tests 1:05 - TID & SEU Test Discussion (Ken LaBel) Cobalt-60 facility and TID testing Non-Goddard facilities and SEU testing 1:10 - Summary (John Damoulakis) 1:15 – General Discussion Q&A

2 Board Need This is a general purpose SEU tester capable of testing digital I/O up to 3GHz ranges. RHBD has a need to test higher bandwidth devices as circuit speeds increase. It will be used to test those circuits that are too fast for the low cost tester. The design, physical board, and a manual will be provided by ISI to the RHBD community.

3 Increasing Clock Speeds Slide Courtesy Ken LaBel NGSFC

4 High Speed Tester Board

5 Requirements High and Low Speed I/O Eight banks of configurable I/O Single ended CMOS 1.5V to CMOS 3.3V levels (configurable via VCCO) Differential LVDS capabilty to 840MB/s (on chip termination) Sixteen High Speed Rocket I/Os (Rocket I/O Gbs) SRAM (1Mx16 identical to Low Speed Tester) Configurable Voltage Supply & Current Telemetry Logic Standards Configurable via VCCO Configurable Voltage Regulator or External Input Power Fet shunt w/ fast comparator for latchup shutoff A/D and D/A converters (same as Spartan3 tester) Clock Speeds Flexible RS232, USB, and Ethernet(looking at)

6 Schedule Long lead parts identified and on order. Design review in late February. H/W design complete by March 1. H/W fabricated and assembled by April 1. Board complete and ready for testing by June 1*. First test target is SDRAM. Follow on Possibilities Unspecified higher speed device Boeing Chips MRC Chips *Assumes firmware complete.

7 Agenda 11:00 - Introduction (Damoulakis) 11:05 - Overview of Test Needs (Ken LaBel) Low Cost Test Needs High Speed Test Needs 11:15 - Team Responsibilities & Partnerships (Jim Howard) Managerial Topics - Team, Responsibilities, Partnerships Testing - How & Why Functional/Facilities/Usage DUT Independence Design Flows 11:35 - Low Cost/Speed Tester (Hak Kim) Design Overview 11:45 - High Speed Tester (Scott Stansberry) Requirements Design Overview Status 12:00 – Lunch (provided) 12:30 - User I/F & VHDL Modules (Charlie) 12:50 - Test Coupons (Valencia Joyner) Describe coupon designs & Tests Describe SEU design & Tests 1:05 - TID & SEU Test Discussion (Ken LaBel) Cobalt-60 facility and TID testing Non-Goddard facilities and SEU testing 1:10 - Summary (John Damoulakis) 1:15 – General Discussion Q&A