Acceleration Sensing Dec 10, 2004 Zhong-Yi Jin William Chang.

Slides:



Advertisements
Similar presentations
Categories of I/O Devices
Advertisements

1 Exceptions, Interrupts & Traps Operating System Hebrew University Spring 2007.
Umut Girit  One of the core members of the Internet Protocol Suite, the set of network protocols used for the Internet. With UDP, computer.
CS-334: Computer Architecture
CMPT 300: Operating Systems I Dr. Mohamed Hefeeda
ECE 526 – Network Processing Systems Design Software-based Protocol Processing Chapter 7: D. E. Comer.
1 School of Computing Science Simon Fraser University CMPT 300: Operating Systems I Dr. Mohamed Hefeeda.
Precept 3 COS 461. Concurrency is Useful Multi Processor/Core Multiple Inputs Don’t wait on slow devices.
1 Soft Timers: Efficient Microsecond Software Timer Support For Network Processing Mohit Aron and Peter Druschel Rice University Presented By Jonathan.
Chapter 1 and 2 Computer System and Operating System Overview
Mehmet Can Vuran, Instructor University of Nebraska-Lincoln Acknowledgement: Overheads adapted from those provided by the authors of the textbook.
1 Today I/O Systems Storage. 2 I/O Devices Many different kinds of I/O devices Software that controls them: device drivers.
Exceptions, Interrupts & Traps
G Robert Grimm New York University Receiver Livelock.
Chapter 31 File Transfer & Remote File Access (NFS)
Introduction to Embedded Systems
3/11/2002CSE Input/Output Input/Output Control Datapath Memory Processor Input Output Memory Input Output Network Control Datapath Processor.
Protection and the Kernel: Mode, Space, and Context.
Acceleration Based Pedometer
Hardware Definitions –Port: Point of connection –Bus: Interface Daisy Chain (A=>B=>…=>X) Shared Direct Device Access –Controller: Device Electronics –Registers:
Interrupts and DMA CSCI The Role of the Operating System in Performing I/O Two main jobs of a computer are: –Processing –Performing I/O manage and.
1-1 Embedded Network Interface (ENI) API Concepts Shared RAM vs. FIFO modes ENI API’s.
EPICS Developments at the Australian Synchrotron DSP EPICS driver for the General Standards 16AIO analog card EPICS driver for the Galil range of motor.
BASS Application Sharing System Omer Boyaci September 10,
Outline Overview Video Format Conversion Connection with An authentication Streaming media Transferring media.
Tami Meredith, Ph.D. CSCI  Devices need CPU access  E.g., NIC has a full buffer it needs to empty  These device needs are often asynchronous.
Computer Communications Sunggu Lee EE Dept., POSTECH Sep. 7, 2006.
Scheduling Lecture 6. What is Scheduling? An O/S often has many pending tasks. –Threads, async callbacks, device input. The order may matter. –Policy,
Time Management.  Time management is concerned with OS facilities and services which measure real time, and is essential to the operation of timesharing.
Hot Interconnects TCP-Splitter: A Reconfigurable Hardware Based TCP/IP Flow Monitor David V. Schuehler
Networking Basics CCNA 1 Chapter 11.
L/O/G/O Input Output Chapter 4 CS.216 Computer Architecture and Organization.
1 Soft Timers: Efficient Microsecond Software Timer Support For Network Processing Mohit Aron and Peter Druschel Rice University Presented By Oindrila.
Processor Architecture
1 Computer Systems II Introduction to Processes. 2 First Two Major Computer System Evolution Steps Led to the idea of multiprogramming (multiple concurrent.
Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower than CPU.
Berkeley Socket Abstraction
Processor Memory Processor-memory bus I/O Device Bus Adapter I/O Device I/O Device Bus Adapter I/O Device I/O Device Expansion bus I/O Bus.
بسم الله الرحمن الرحيم MEMORY AND I/O.
Time Management.  Time management is concerned with OS facilities and services which measure real time.  These services include:  Keeping track of.
Slides created by: Professor Ian G. Harris Operating Systems  Allow the processor to perform several tasks at virtually the same time Ex. Web Controlled.
By Nitin Bahadur Gokul Nadathur Department of Computer Sciences University of Wisconsin-Madison Spring 2000.
1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.
Interrupts and Exception Handling. Execution We are quite aware of the Fetch, Execute process of the control unit of the CPU –Fetch and instruction as.
TCP/IP1 Address Resolution Protocol Internet uses IP address to recognize a computer. But IP address needs to be translated to physical address (NIC).
1 Network Communications A Brief Introduction. 2 Network Communications.
Embedded Real-Time Systems Processing interrupts Lecturer Department University.
1 Chapter 2: Operating-System Structures Services Interface provided to users & programmers –System calls (programmer access) –User level access to system.
Soft Timers : Efficient Microsecond Software Timer Support for Network Processing - Mohit Aron & Peter Druschel CS533 Winter 2007.
Introduction to Operating Systems Concepts
Operating System Overview
The Transport Layer Congestion Control & UDP
Processes and threads.
Threads vs. Events SEDA – An Event Model 5204 – Operating Systems.
Interrupts and signals
CS501 Advanced Computer Architecture
CS 6560: Operating Systems Design
Timer and Interrupts.
Mechanism: Limited Direct Execution
Presented by Kristen Carlson Accardi
Operating Systems (CS 340 D)
CS703 - Advanced Operating Systems
Direct Memory Access Disk and Network transfers: awkward timing:
Lecture Topics: 11/1 General Operating System Concepts Processes
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
Chapter 13: I/O Systems I/O Hardware Application I/O Interface
The Transport Layer Chapter 6.
Chapter 13: I/O Systems.
Presentation transcript:

Acceleration Sensing Dec 10, 2004 Zhong-Yi Jin William Chang

Introduction Motivation: Motion Tracking Hardwares DPAC Airborne Wireless Node Module Analog Devices 2D  5g Accelerometer b Wireless Access Point

Goals Interface Accelerometer Sensor to the DPAC Module Sample Sensor Data Process Acceleration Data Present Data

DPAC Board Client 1: Establish TCP Connection 3way Handshaking 2: Send Request: Eg: “Read Port G0” 3: Interpret Request, read data from G0 Acc eler ome ter G0 4: Send data back G1G2 S er v er G3 DPAC Preloaded Software Problem: Crash if client try to send request at a rate more than 25HZ !!!

What Happened? No source code for the Preloaded DPAC server. A black box. Have to experiment and observer. The faster we send request, the quicker the server will crash If send request slowly, everything fine We must have somehow saturated the server with too many requests. But 25 Hz is so slow!

Not efficient to send request for every read DPACClientDPACClient Old ApproachNew Approach 1)Needs allocate memory for incoming packets 2)Needs CPU time to unpack packet from each layer. 3)Needs CPU time to interpret the request.

Waste bandwidth by Not having enough data in one packet Combine multiple samples into one packet Will introduce latency Nagle ’ s algorithm? Old ApproachNew Approach HH Payload HH

Not Real time Data (10bits) Time Stamp Old ApproachNew Approach 16 bits16 Bits 1)TCP and b is not real time by natural (interference retransmission) 2) Time stamp records the time right before the data is being read from the accelerometer. 3) Provides extra information for client to detect problems.

IPOS Startup Code a. The FCFG register is updated so that code execution speed is optimized for the clock frequency. b. The stack pointer is set to point to the end of the data memory. c. start_filemedia_init() is called to initialize the filesystem if FILEMEDIA_SUPPORT is defined. d. The.pram section is loaded from flash to the start of the program SRAM. e. An area of program SRAM is set to zeros to accomodate the.pram_data section. f. start_init_ip2kvm() is called to load ip2kvm external memory g. The.data section is loaded from the flash to the start of the data memory. h. An area of data memory is set to zeros after the.data section, to accomodate the.bss section. i. The general purpose registers are initialized to zero. j. The bootstrap code is complete and it jumps to system_main() which is a weak alias for a call to main() which is retained for backwards compatibility with versions prior to 5.0. k. system_main will call the user's 'init()' and 'start()' routines prior to entering an inner system polling loop for which the user may registered to be polled.

IPOS Scheduler callback //excerpt form iphal/src/ip2k/system.c { /* * System Loop */ except_try { while (TRUE) { watchdog_reset(); event_notify(system_event_poll, 0); } except_catch(ex) { DEBUG_ASSERT(0, "unhandled exception"); system_reset(); } System Event Pool 1) A single program approach in core. 2) Hide the loop in the system_main

IPOS Timer callback Timer callback callback System Event Pool Callback Expire 20 Call back Expire 10 Timer Event Pool System Clock = 5 Call back Expire 5

IPOS Interrupt Interrupt handlers will always run to completion Uses shadow registers for ISR context switch => context switch time is fast and predictable Can ’ t be used to implement foreground/background system since context switch from interrupt service routine to a task other than the one originally being interrupted would flush the shadow registers and thus the original task won ’ t be able to run again after the return of ISR

Implementation EventsCallbacks(Descriptions) 1SystemEv ent telnet_app_connect/telnet_app_close (Listens For new connection or disconnection) 2SystemEv ent telnet_app_recv (Processes requests from existing connections, including requests for application level disconnection). Request will specify what data to read, at what frequency and how many data should be delivered at once in one TCP packet. Through out this report, the number of samples to put into one packet for delivery is called piggyback factor.) 3OneShot Timer Event adcCallback (Reads data from specified IO at the specified frequencies. Piggyback multiple data into one packet.) 4OneShot Timer Event adcCallback (Send packet with data as payload back to the client, at the specified frequency and piggyback factor)

Results 1) Sustained sampling rate of 1000 Hz (1000Hz + 20 Piggyback factor) is achieved. 3 Hours of test, no missing or out of order time stamp. 40 Times Better than DPAC 2) Returned Packet Rate = Sampling Frequency / Piggyback Factor Min Piggyback = 3  Max Returned Packet Rate = 1000/3 = 333 TCP Packet/ Second 3) Typical TCP packet has payload of 1460 bytes. Thus, we have Max theoretical Throughput Rate = 1460 * 333/Second = Bytes/Second = 3.7Mbits/Second

Client Application DPAC Module Connection Data Calibration Data Processing Compute Voltage Compute Acceleration Noise Reduction Data Display

DPAC Module Connection Using TCP/IP on b Wireless Protocol Java.net.Socket on Static IP & Port 23 Request Command: “ o ” vs. “ w ”

Data Processing Data Format 2 byte data (6 bits timestamp + 10 bits data) Voltage Computation V = (Data / 1022) x 2.5 Acceleration Computation g = (V – V 0 ) x 1000 / ratio Noise Reduction average of samples

Data Calibration 0g Calibration  1g Calibration Conversion Ratios mV/g = (V max - V 0 ) x 1000 mV/g = (V 0 - V min ) x 1000

Application Implementation Java Program Thread 1: DPAC Interface Connect to the DPAC Module Calibrate Data Process Data Stream Thread 2: Display Using AWT Library

Demo

Q & A

Thank You