Chapter 1 — Computer Abstractions and Technology — 1 Uniprocessor Performance Constrained by power, instruction-level parallelism, memory latency.

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Presentation transcript:

Chapter 1 — Computer Abstractions and Technology — 1 Uniprocessor Performance Constrained by power, instruction-level parallelism, memory latency

Chapter 1 — Computer Abstractions and Technology — 2 Multiprocessors Multicore microprocessors – More than one processor per chip Requires explicitly parallel programming – Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer – Hard to do Programming for performance Load balancing Optimizing communication and synchronization

Chapter 1 — Computer Abstractions and Technology — 3 SPEC CPU Benchmark Programs used to measure performance – Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC) – Develops benchmarks for CPU, I/O, Web, … SPEC CPU2006 – Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance – Normalize relative to reference machine – Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point)

Semiconductor Technology Silicon: semiconductor Add materials to transform properties: – Conductors – Insulators – Switch Chapter 1 — Computer Abstractions and Technology — 4

Chapter 1 — Computer Abstractions and Technology — 5 Manufacturing ICs Yield: proportion of working dies per wafer

Chapter 1 — Computer Abstractions and Technology — 6 CINT2006 for Intel Core i7 920

Chapter 1 — Computer Abstractions and Technology — 7 Intel Core i7 Wafer 300mm wafer, 280 chips, 32nm technology Each chip is 20.7 x 10.5 mm

Chapter 1 — Computer Abstractions and Technology — 8 SPEC Power Benchmark Power consumption of server at different workload levels – Performance: ssj_ops/sec – Power: Watts (Joules/sec)

Chapter 1 — Computer Abstractions and Technology — 9 Integrated Circuit Cost Nonlinear relation to area and defect rate – Wafer cost and area are fixed – Defect rate determined by manufacturing process – Die area determined by architecture and circuit design

Chapter 1 — Computer Abstractions and Technology — 10 SPECpower_ssj2008 for Xeon X5650

Chapter 1 — Computer Abstractions and Technology — 11 Pitfall: Amdahl’s Law Improving an aspect of a computer and expecting a proportional improvement in overall performance Can’t be done! Example: multiply accounts for 80s/100s How much improvement in multiply performance to get 5× overall? Corollary: make the common case fast

Chapter 1 — Computer Abstractions and Technology — 12 Fallacy: Low Power at Idle Look back at i7 power benchmark – At 100% load: 258W – At 50% load: 170W (66%) – At 10% load: 121W (47%) Google data center – Mostly operates at 10% – 50% load – At 100% load less than 1% of the time Consider designing processors to make power proportional to load

Chapter 1 — Computer Abstractions and Technology — 13 Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second – Doesn’t account for Differences in ISAs between computers Differences in complexity between instructions CPI varies between programs on a given CPU