W ORST -C ASE N OISE A REA P REDICTION OF O N -C HIP P OWER D ISTRIBUTION N ETWORK Xiang Zhang 1, Jingwei Lu 2, Yang Liu 3 and Chung-Kuan Cheng 1,2 1 ECE Dept., University of California, San Diego, CA, USA 2 CSE Dept., University of California, San Diego, CA, USA 3 Institute of Electronic CAD, Xidian University, Xi’an, China

E XECUTIVE S UMMARY Problem: Previous works focus on the worst-peak droop to sign off PDN. Worst-peak noise ≠ Worst timing (delay) Our goal: To predict a PDN noise for better timing sign off. Observation: The noise area of PDN => Behavior of circuit delay Case study: Design the worst-case PDN noise area Provide analytical solution for a lumped PDN model Design an algorithm for general PDN cases Results: Worst-area noise introduces 1.8% additional propagation delay compared to worst-peak noise from our empirical validation under a complete PDN path. 2

P OWER D ISTRIBUTION N ETWORK (PDN) Power supply noise Resistive IR drop Inductive Ldi/dt noise PDN model 3

M OTIVATION Performance sensitivity on PDN voltage drop Increased signal delay [Saint-Laurent’04] [Jiang’99] Clock jitter [Pialis’03] Delay vs supply voltage(courtesy of [Saint-Laurent’04]) 4

PDN N OISE A REA VS D ELAY Delay is measured under a modified C432 of ISCAS85 circuit in 130nm node 5

P ROBLEM F ORMULATION PDN Characterization Impulse Response h(t) Voltage Noise: Input to PDN system Transient load current demand i(t) Assumption: All on-die loads lumped into a single load Total current is bounded 6

P ROBLEM F ORMULATION 7

P ROBLEM S IMPLIFICATION 8

S IMPLIFIED P ROBLEM F ORMULATION 9

C ASE S TUDY : RLC T ANK M ODEL 10

W ORST N OISE A REA P REDICTION FOR RLC T ANK 11

C ASE S TUDY : W ORST N OISE A REA P REDICTION FOR G ENERAL PDN C ASES 12

I NTUITION 13

A LGORITHM D ESIGN 14

C OMPLEXITY A NALYSIS Our algorithm consists of finite operations Step response transformation Linear scan for peaks & valleys extraction Worst-case current construction Overall complexity is O(n) Finite amount of operations Each operation consumes no larger than linear runtime 15

E XPERIMENTAL D ESIGN AND R ESULTS Setup: Matlab R2013a HSPICE D SP1 Cadence Allegro Sigrity Power SI 16.6 Ansoft Q3D 12.0 ISCAS85 circuit under 0.13um cell lib Intel i7 Qual-Core 3.4GHz w/16GB PCDDR3 PDN test cases Single RLC tank Cascaded RLC tanks A complete PDN path extracted from industrial design 16

W ORST -P EAK AND W ORST -A REA N OISE OF A S INGLE RLC T ANK C ASE 17

W ORST -A REA AND W ORST -P EAK N OISE OF M ULTI -S TAGE C ASCADED RLC T ANKS Circuit Model Three Cases Case I can be approximated to three single RLC tanks: 18

W ORST -A REA AND W ORST -P EAK N OISES OF M ULTI -S TAGE C ASCADED RLC T ANKS 19

W ORST -P EAK AND W ORST -A REA N OISE OF A C OMPLETE PDN P ATH Impedance Profile: 20

W ORST -P EAK AND W ORST -A REA N OISE OF A C OMPLETE PDN P ATH 21

D ELAY M EASUREMENT OF A C OMPLETE PDN P ATH Send input pulse every 100ps and record delay of the datapath at the output port of C432 (ISCAS85) case Compare the delay under worst-peak and worst-area noise Results: 22

C ONCLUSIONS Problem: Previous works focus on the worst-peak droop to sign off PDN. Worst-peak noise ≠ Worst timing (delay) Our goal: To predict a PDN noise for better timing sign off. Observation: The noise area of PDN => Behavior of circuit delay Case study: Design the worst-case PDN noise area Provide analytical solution for a lumped PDN model Design an algorithm for general PDN cases Results: Worst-area noise introduces 1.8% additional propagation delay compared to worst-peak noise from our empirical validation under a complete PDN path. 23

Q & A 24

25

D ELAY M EASUREMENT OF S INGLE RLC T ANK C ASE Send input pulse every 100ps and record delay of the datapath at the output port of C432 (ISCAS85) case 26