Dr. Turki F. Al-Somani VHDL synthesis and simulation

2 Combinational logic design A) Problem description y is 1 if a is to 1, or b and c are 1. z is 1 if b or c is to 1, but not both, or if all are 1. D) Minimized output equations a bc y y = a + bc z z = ab + b’c + bc’ a bc C) Output equations y = a'bc + ab'c' + ab'c + abc' + abc z = a'b'c + a'bc' + ab'c + abc' + abc B) Truth table Inputs abc Outputs yz E) Logic Gates a b c y z

3 Sequential logic design A) Problem Description You want to construct a clock divider. Slow down your pre- existing clock so that you output a 1 for every four clock cycles x=0 x=1 x=0 a=1 a=0 B) State DiagramC) Implementation Model Combinational logic State register a x I0 I1 Q1 Q0 D) State Table (Moore-type) Inputs Q1Q0a Outputs I1I x  Given this implementation model Sequential logic design quickly reduces to combinational logic design

4 Sequential logic design (cont.) Q1Q0 I1 I1 = Q1’Q0a + Q1a’ + Q1Q0’ a a 1 10 I0 Q1Q0 I0 = Q0a’ + Q0’a x = Q1Q0 x a Q1Q0 E) Minimized Output EquationsF) Combinational Logic a Q1 Q0 I0 I1 x

5 Custom single-purpose processor basic model controller and datapath controllerdatapath … … external control inputs external control outputs … external data inputs … external data outputs datapath control inputs datapath control outputs … … a view inside the controller and datapath controllerdatapath … … state register next-state and control logic registers functional units

6 Example: greatest common divisor GCD (a) black-box view x_i y_i d_o go_i 0: int x, y; 1: while (1) { 2: while (!go_i); 3: x = x_i; 4: y = y_i; 5: while (x != y) { 6: if (x < y) 7: y = y - x; else 8: x = x - y; } 9: d_o = x; } (b) desired functionality y = y -x 7: x = x - y 8: 6-J: x!=y 5: !(x!=y) x<y!(x<y) 6: 5-J: 1: 1 !1 x = x_i 3: y = y_i 4: 2: 2-J: !go_i !(!go_i) d_o = x 1-J: 9: (c) state diagram  First create algorithm  Convert algorithm to “complex” state machine Known as FSMD: finite- state machine with datapath Can use templates to perform such conversion

7 Creating the datapath  Create a register for any declared variable  Create a functional unit for each arithmetic operation  Connect the ports, registers and functional units Based on reads and writes Use multiplexors for multiple sources  Create unique identifier for each datapath component control input and output y = y -x 7: x = x - y 8: 6-J: x!=y 5: !(x!=y) x<y!(x<y) 6: 5-J: 1: 1 !1 x = x_i 3: y = y_i 4: 2: 2-J: !go_i !(!go_i) d_o = x 1-J: 9: subtractor 7: y-x8: x-y5: x!=y6: x<y x_iy_i d_o 0: x0: y 9: d n-bit 2x1 x_sel y_sel x_ld y_ld x_neq_y x_lt_y d_ld < 5: x!=y != Datapath

8 Creating the controller’s FSM  Same structure as FSMD  Replace complex actions/conditions with datapath configurations y = y -x 7: x = x - y 8: 6-J: x!=y 5: !(x!=y) x<y!(x<y) 6: 5-J: 1: 1 !1 x = x_i 3: y = y_i 4: 2: 2-J: !go_i !(!go_i) d_o = x 1-J: 9: y_sel = 1 y_ld = 1 7: x_sel = 1 x_ld = 1 8: 6-J: x_neq_y 5: !x_neq_y x_lt_y!x_lt_y 6: 5-J: d_ld = 1 1-J: 9: x_sel = 0 x_ld = 1 3: y_sel = 0 y_ld = 1 4: 1: 1 !1 2: 2-J: !go_i !(!go_i) go_i Controller subtractor 7: y-x8: x-y5: x!=y6: x<y x_iy_i d_o 0: x0: y 9: d n-bit 2x1 x_sel y_sel x_ld y_ld x_neq_y x_lt_y d_ld < 5: x!=y != Datapath

9 Splitting into a controller and datapath y_sel = 1 y_ld = 1 7: x_sel = 1 x_ld = 1 8: 6-J: x_neq_y=1 5: x_neq_y=0 x_lt_y=1x_lt_y=0 6: 5-J: d_ld = 1 1-J: 9: x_sel = 0 x_ld = 1 3: y_sel = 0 y_ld = 1 4: 1: 1 !1 2: 2-J: !go_i !(!go_i) go_i Controller Controller implementation model y_sel x_sel Combinational logic Q3Q0 State register go_i x_neq_y x_lt_y x_ld y_ld d_ld Q2Q1 I3I0I2I1 subtractor 7: y-x8: x-y5: x!=y6: x<y x_iy_i d_o 0: x0: y 9: d n-bit 2x1 x_sel y_sel x_ld y_ld x_neq_y x_lt_y d_ld < 5: x!=y != (b) Datapath

10 Controller state table for the GCD example InputsOutputs Q3Q2Q1Q0x_neq _y x_lt_ y go_iI3I2I1I0x_sely_selx_ldy_ldd_ld 0000***0001XX **00010XX **10011XX ***0001XX ***01000X ***0101X **1011XX **0110XX *0*1000XX *1*0111XX ***1001X ***10011X ***1010XX ***0101XX ***1100XX ***0000XX ***0000XX ***0000XX ***0000XX000

11 Completing the GCD custom single- purpose processor design  We finished the datapath  We have a state table for the next state and control logic All that’s left is combinational logic design  This is not an optimized design, but we see the basic steps … … a view inside the controller and datapath controllerdatapath … … state register next-state and control logic registers functional units

VHDL Part 3 12 Example  Consider the following algorithm that gives the maximum of two numbers. 0: int x, y, z; 1: while (1) { 2: while (!start); 3: x = A; 4: y = B; 5: if (x >= y) 6: z = x; else 7: z = y; }

VHDL Part 3 13 Example – Cont.  Now, consider the following VHDL code that gives the maximum of two numbers entity MAX is generic(size: integer:=4); port( clk, reset, start: in std_logic; x_i, y_i :in std_logic_vector(size-1 downto 0); z_o: out std_logic_vector(size-1 downto 0)); end MAX; architecture behavioral of MAX is type STATE_TYPE is (S0, S1, S2, S3, S4); signal Current_State, Next_State: STATE_TYPE; signal x, y, mux : std_logic_vector (size-1 downto 0):= (others => '0'); signal z_sel, x_ld, y_ld, z_ld : std_logic := '0'; begin

VHDL Part 3 14 Example – Cont Reg_x: process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then x '0'); else if (x_ld='1') then x <= x_i; end if; end process; Reg_y: process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then y '0'); else if (y_ld='1') then y <= y_i; end if; end process; Reg_z_o:process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then z_o '0'); else if (z_ld='1') then z_o <= mux; end if; end process; Multiplexer: process (x, y, z_sel) begin if (z_sel='0') then mux <= x; elsif (z_sel='1') then mux <= y; end if; end process;

VHDL Part 3 15 Example – Cont SYNC_PROC: process (CLK, RESET) begin if (RESET='1') then Current_State <= S0; elsif (CLK'event and CLK = '1') then Current_State <= Next_State; end if; end process; COMB_PROC: process (Current_State, start, x, y, z_sel) begin case Current_State is when S0 =>-- idle if (start='1') then Next_State <= S1; else Next_State <= S0; end if; when S1 =>-- x = x_i & y = y_i x_ld <= '1'; y_ld <= '1'; z_ld <= '0' Next_State <= S2; when S2 =>-- x ≥ y x_ld <= '0'; y_ld <= '0'; if (x >= y ) then Next_State <= S3; else Next_State <= S4; end if; when S3 =>-- z = x z_sel <= '0'; z_ld<=’1’; Next_State <= S0; when S4 =>-- z = y z_sel <= '1'; z_ld<=’1’; Next_State <= S0; end case; end process;

VHDL Part 3 16 Now, What’s Next ?!