Tracker Week February presented by John Coughlan RAL FED Status FEDv2 Testing Pre-Series Manufacture Final Production Plans

Tracker Week February S-LINK Tests Set ups at RAL & IC 4 FED Testers -> 1 FED Transition Card + SLINK TCS Throttle Simulate LHC conditions Random triggers 100kHz Zero Suppressed Data Variable Hit Occupancy Raw low rates Additional Equipment still needed for “Full Crate of FEDs” Test in March Rack with Cooling 2nd LHC 9U Crate & SBS Crate Controller (PCI-X)

Tracker Week February S-LINK Test setup Slink Rx Generic PCI Card Slink PC (PCI-X slots) Access VME with SBS620 PCI-VME link LVDS cable FED Simulate Local Trigger Control System FT (master) FT (slave) Slink-Tx Clock & L1As from FT to FED Throttle signals from FED to FT Merge 96 fibres into 8 ribbons of 12 fibres J0 Connector J1 Connector VME crate J2 Connector “James Leaver & Greg Iles”

Tracker Week February Pedestal Noise Simple noise measurement: Disabled FED Tester output and set appropriate FED TrimDAC / OptoRx values (constant across all channels) Captured a Scope Mode event for each FED channel (Scope Length = 1020) Found mean and standard deviation of signal at each channel: Analysis by James Leaver Imperial College

Tracker Week February Cross-Talk Pulse 2: Nearest Neighbour Pulse 3: Nearest Neighbour

Tracker Week February Single Hit Finding All invalid ‘hits’ have vanished Result: FED is correctly identifying all input hits

Tracker Week February Test Results FED Crosstalk: FED Crosstalk: Unpleasant effects when a single frame arrives at the FED out of sync with the others… …But crosstalk caused by ‘hit’ features is small and should only impact nearest neighbours FED Channel Noise: FED Channel Noise: Average noise is less than 1 ADC count, with no significant variation from channel to channel FED Hit Check: FED Hit Check: FED correctly identifies hits in Zero Suppressed mode (for a 2% Tracker occupancy) FED Efficiency: FED Efficiency: FED vetoes triggers at high data rates in a similar manner to that predicted by Simulation studies, but Zero Suppressed ‘Lite’ mode required for genuine CMS performance characterisation Measured data rates show reasonable agreement with theory, but a more accurate cluster distribution is required Analysis by James Leaver Imperial College

Tracker Week February FEDv2 Pre-Series Pre-Series Schedule Q3/2004 : Manufacture and commission 2 FEDv2s. Done. Q4/2004 : Prepare pre-series production of 25 FEDv2 boards. Final tests of FEDv2 design: Fast readout with S-LINK working. Done. Fine tuning of Front-End analogue passive components. Change Rload = 62R (to be verified on FEDv2). Second iteration of board design FEDv2 should be FINAL. Q1/2005 : Pre-series of (to verify full VME crate operation and then deliver to LSA centres)  5 boards delivered to RAL last week. first 5 pcbs had problems with metal surface finish and had to be replaced before assembly. quality of assembled boards so far has been excellent 4 assembled boards are “perfect”. 1 has a single fault under investigation.  20 further boards in 4 batches to be delivered to RAL during March. Q2/2005 Full crate tests est. 6 weeks. If ok start FED deliveries to CERN in May. Equipment Missing : 2 nd LHC 9U crate and Crate Controller. Replace FEDv1s with FEDv2s. Minimises our maintenance effort.

Tracker Week February FE Analogue Performance CMS Internal Note in preparation Stefan Dris CERN Gain adjustment Rload 100 –> 62 Ohm

Tracker Week February FED Final Production Final Production Schedule Q3/2004 : EU Tender for PCB & Assembly. Done. Q4/2004 : Company selection (DDi Technologies Europe Ltd). Done. Obtain Quotes including CMS custom Testing at Assembly plant. Done. Q1/2005 : Submission to CERN Finance Committee. Arrange procedures between CERN (on behalf of CMS FAs) and RAL. Q2/2005 : Sign formal contract with DDi. Starts procurement. Q3/2005 -> Q3/2006 : Manufacture 500 ~ 50 / month. Fully test boards in UK. At Assembly Plant and at RAL. Ship to CERN B904; re-test full crates and store until USC55 available.

Tracker Week February Validation Testing at Assembly Plant 1. Custom Tests at Assembly Plant BScan, VME crate 3. Tests at CERN Prevessin 904 DAQ Integration 2. Tests at RAL & IC OptoRx, Full crate 4. Installation at CMS USC55 0. Quality Controls during Assembly process AOI, X-ray VME Crate Testing for Analogue Test Flow from Assembly Plant to USC boards to test over 10 months. Essential to catch any manufacturing faults early. Boundary Scan Testing for Digital Testing by Assembly plant operatives

Tracker Week February FED web pages

Tracker Week February End Last Slide

Tracker Week February Full Debug Mode

Tracker Week February APV Error Mode

Tracker Week February FEDv2 pre-Production Board Aim to be final production version - minimal changes from v1  Power Block : General improvements.  QDR Memory : Replacement part (pin compatible) identified and on order.  FE FPGA : Use larger 2M gate (pin compatible) part.  ADC : AD9218 Device bug. Reduce gain by half. Simple mod.  FPGA Configuration : Boot device reprogram via VME J0 / JTAG cable.  S-LINK & TCS Signals : New 6U VME Transition Card.  FE Analogue : Tune few components for optimal matching to Optical Link Status First 2 boards received in August as scheduled. Tests proceeding well. Boundary Scan passed. VME based readout tests working. S-LINK tests in progress with new Transition card.  Plan to make a further ~20 at end of 2004 for Full Crate tests.

Tracker Week February FED Status

Tracker Week February Efficiency Events lost when occupancy exceeds ~2.8% with 200 MB/s readout rate But Header Data is much LARGER than in final system!