CERN, CT Workshop, ID Week, July 2 nd, 2007 Connectivity Workshop Conclusions: Lessons learned C12 Test Next future Claudia Gemme, CERN - INFN Genova Connectivity Workshop Conclusions: Lessons learned C12 Test Next future Claudia Gemme, CERN - INFN Genova

2 2 First SQP (C34) was shipped to SR1 from Bat 154 on 22 Feb. The Connectivity Test was an effort that a large part of the Pixel community supported for more than 3 months, involving many people from DAQ, DCS, mechanics, optolinks experts other than the CT crew itself (11 shifters). Operation required 7 days week and long working hours to fit the schedule; DAQ and DCS permanently on call -> and quite unusually we finished perfectly in time! Other than testing and qualification of the Pixel Package, an important and not secondary outcome is that many people were involved in the actual running of the detector and now know how to basically control DAQ, DCS and the detector itself.

3 3 Test on the first SQP C34Inner started indeed 28 Feb! Up to 21 Mar we work to test and improve our tools: Sequence of tests and integration Test optoheaters Test sense lines SIT mapping Optolink fiber mapping Database issues… -21!! Test of A34 started on 22 March with much better tools. With red arrows the most problematic SQPs. On A34 we had to give up and we tested it again at the end of the integration.

4 4 Lessons learned: Hardware Mapping MT16/MT8 mapping from PP0 to PP1: it was not completely traced in 154 and not included in any database that routed directly from PP0 to BOC plugin. Based on the measured connectivity we did, we are now starting the fiber allocation in the pit crates. Detector final mapping has few unconformities with respect to the original mapping. This is the starting point for the detector services. Failures in the type 0 cables were not where we expected to find them -> fine for the future. Higher sense lines resistance in L2 cables have been fixed but it could be a on-going process. Experience in debugging problems has greatly increased during testing time as the system knowledge was increasing. For instance: to fix the ROD problem (no DCI in one channel) it took three SQPs! debug of no PIN current in the optoboard has now a more clear debug procedure.

5 5 Optoboards operation Optoboards have been tuned relatively easily: the boards selection in 154 has improved since the system test and they were running rather hot (25-35C). Gained significant tuning experience at 40Mbit/s, 80Mbit/s, and 160 MBit/s and developed software to deal it. Extensive comparison of clocked opto-link (Fast) versus short pseudo-random sequence (Slow): some indication of “slot turn- on” effects seen and correlated with 154 measurement -> see Beate’s talk. But no problem in operation. No full optoboard failure but unexplained death of one PIN channel (never observed before) and VCSEL (one failure in 154) No hints of CommonSeriesResistance aging process.

6 6 Some additional problems observed occasionally in module digital scans are not yet fully understood, (see Andreas’s talk) but appear un-related to opto-link parameters. We succefully operated 20 RODs in 2 crates. Full parallelization was not possible only because the detector had no cooling but it has been proved to be possible.

7 7 Lessons learned: software We have done big improvements in DAQ during the Connectivity Test (see DAQ session): DAQ-DCS-Communication was extensively used CoralDb/Oracle connectivity database Module configuration in RootDB Machinery to create the xml files for the SIT mapping CT code However online analysis was poor and we needed to check summary results by eye. Output file format has been fixed only at the 5 th SQP as code and procedure kept having major updates since then. The main problem was that we had to manage two opposite needs: testing the detector in time for the installation (need a stable code and a stable procedure) and develop the code to more stable/efficient releases. The result was often confusing.

8 8 C12 test in SR1 This was a realistic test of connections (electrical, optical and cooling) of PP1 region using C12 quadrant. Setup of “dummy PP1 region” at C-side of DST, near System Test services Mock up approximate geometry of nose region, and bundle SR1 System Test cables as done on the flange in the pit. Full report of the 5 working days by Maurice on the detector e-log Test done at any stage: Type 1 cable in panels While connecting Type 2 cables After fiber connection

9 9 Unfolding electrical services First step is unfolding of electrical services to form PP1b using corrugated panels. This was more complicated than expected and took 2 days to find an optimal solution. 1. Cut back of outer panel to allow routing cables to the back of the nose 2. Shifted all connectors on rows 1 and 5 towards cable source in order to have the empty slot (these rows always have an empty) in the longest cable position. 3. Left-right swapped outer panel connector pairs whenever is possible to match what was erroneously done in the pit with the PP2 cables (already dressed). Only 3 pairs need to be handled by crossing PP2 cables. This solution seems fine for the pit even if any quadrant may be slightly different. Estimate in UX15 is roughly one day per octant.

10 Whenever all the type 1 cables were allocated in the corrugated panel, a test was performed to verify the connections. The most fragile parts are the solderings on the penetration cards that should be better fixed while cabling. LV Type1 cables were tested with the Keithley sense setups (it is a complete check). NTC were tested by using Type2 cable of the bistave setup as it was available. This will not be possible in the pit. HV Type1: No test.

11 Connection of Type 2 cables Type 2 cables were bundled and routed as on flange as it is in the pit. Same “dummy” heaters were used to define a safe envelope around where real heaters will go. Some preliminary electrical tests have been done during the connection. It is important to know at this stage if the match is right and the connection is working. NTC: check NTC are all connected. Switch on Viset and Vpin (we will try to inject light at PP1 to measure some PIN current). OptoRST not measurable. We did it by eye with the FSM panels but we will do it as a Phase1 test. HV: switch on high voltage and measure currents (we could ramp to 600V) LV: run a phase1-no opto.

12 We have just realized that connecting by row (NTC first, the HV, last LV) is not easy and we will connect by position. LV can be tested only if ‘their’ NTC is already plugged in.

13 Connectivity Test Bucket was removed and fibers plugged in (but not routed in the proper place). Fibers run at smaller radius than Type 2 cables. Both cables and fiber will be trapped by pipe connections.

14 Connectivity Test For the full qualification of the cable connection, fibers are needed. The proposed test is: Phase1 i.e. measure voltages, currents and temperatures of modules and optoboards. It checks also that the TTC fibers are fine as measures the PIN current and the presence of clock in the modules. Phase2: link test or power measurement to check that the DATA fibers are fine. FastTuning in the pit. Phase3 Threshold scan to measure noise for few pixels in each module to be sure that the HV is provided to each sensor. BOC setting obtained during the CT were used. It took less then 6 hours to run the CT on C2 (18 boards)

15 Next future Unfolding services will start next week and wiil take four weeks. Maps have to be prepared to plug type 1 cables in the corrugated panels following the experience of C12 mockup. Due to the big delay between the unfolding and the connection of type 2 cables (October?), we will certainly be interested to know something more on the status of the detector. So we expect to run, other than the sense test to check the LV cables, some more test on the NTC and on the HV. Then we will have time to prepare the connectivity test with the final services, optolinks, DAQ and DCS better support to operate the detector for the first time.