Lecture #10 Page 1 Lecture #10 Agenda 1.VHDL : Concurrent Signal Assignments 2.Decoders using Structural VHDL Announcements 1.HW #4 due 2.HW #5 assigned.

Slides:

Advertisements

Similar presentations

Advertisements

©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.

EE 261 – Introduction to Logic Circuits

VHDL Refresher ECE 437 April 13, 2015 Motivation ECE 337 is a prerequisite But… –You may have taken 337 a few semesters previous –Breaks causes memory.

Supplement on Verilog adder examples

EELE 367 – Logic Design Module 4 – Combinational Logic Design with VHDL Agenda 1.Decoders/Encoders 2.Multiplexers/Demultiplexers 3.Tri-State Buffers 4.Comparators.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

EE 261 – Introduction to Logic Circuits Module #5 Page 1 EE 261 – Introduction to Logic Circuits Module #5 - VHDL Topics A.Hardware Description Languages.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/ R.H.Khade.

EE 367 – Logic Design Lecture #17

CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Behavioral & Structural.

Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design.

ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.

Data Flow Modeling of Combinational Logic Simple Testbenches

ENG6090 RCS1 ENG6090 Reconfigurable Computing Systems Hardware Description Languages Part 4: Modeling Dataflow.

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.

Tutorial 1 Combinational Logic Synthesis. Introduction to VHDL VHDL = Very high speed Hardware Description Language VHDL and Verilog are the industry.

ENG241 Digital Design Week #4 Combinational Logic Design.

ECE Advanced Digital Systems Design Lecture 4 – Combinational Circuits in VHDL Capt Michael Tanner Room 2F46A HQ U.S. Air Force Academy.

Basic Overview of VHDL Matthew Murach Slides Available at:

2-Jun-16EE5141 Chapter 3 ä The concept of the signal ä Process concurrency ä Delta time ä Concurrent and sequential statements ä Process activation by.

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Digital Logic Design.

Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.

ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

IAY 0600 Digital Systems Design VHDL discussion Dataflow Style Combinational Design Alexander Sudnitson Tallinn University of Technology.

Lecture #9 Page 1 Lecture #9 Agenda 1.VHDL : Structural Design Announcements 1.n/a ECE 4110– Digital Logic Design.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, February 25 CEC 220 Digital Circuit Design Slide 1 of 19.

George Mason University Data Flow Modeling in VHDL ECE 545 Lecture 7.

Lecture #18 Page 1 ECE 4110– Sequential Logic Design Lecture #18 Agenda 1.MSI Demultiplexers 2.MSI Tri-State Buffers 3.MSI Comparators Announcements 1.HW.

9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends.

CS/EE 3700 : Fundamentals of Digital System Design

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

ECOM 4311—Digital System Design with VHDL

Data Flow Modeling in VHDL

Apr. 3, 2000Systems Architecture I1 Introduction to VHDL (CS 570) Jeremy R. Johnson Wed. Nov. 8, 2000.

CEC 220 Digital Circuit Design Introduction to VHDL Friday, February 21 CEC 220 Digital Circuit Design Slide 1 of 10.

May 9, 2001Systems Architecture I1 Systems Architecture I (CS ) Lab 5: Introduction to VHDL Jeremy R. Johnson May 9, 2001.

RTL Hardware Design Chapter Combinational versus sequential circuit 2. Simple signal assignment statement 3. Conditional signal assignment statement.

COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design Slide 1 of 19.

Lecture #17 Page 1 ECE 4110–5110 Digital System Design Lecture #17 Agenda 1.MSI Multiplexers 2.MSI Encoders Announcements Test 1 closed book, Wednesday.

George Mason University Data Flow Modeling of Combinational Logic ECE 545 Lecture 5.

Lecture #12 Page 1 ECE 4110– Digital Logic Design Lecture #12 Agenda 1.VHDL : Behavioral Design (Processes) Announcements 1.n/a.

Lecture #18 Page 1 ECE 4110–5110 Digital System Design Lecture #18 Agenda 1.MSI Demultiplexers 2.MSI Tri-State Buffers 3.MSI Comparators Announcements.

Lecture #11 Page 1 Lecture #11 Agenda 1.Decoders using Structural VHDL 2.VHDL : Generics and Constants Announcements 1.n/a ECE 4110– Digital Logic Design.

ECE 4110–5110 Digital System Design

Systems Architecture Lab: Introduction to VHDL

Describing Combinational Logic Using Processes

ECE 4110–5110 Digital System Design

ECE 4110–5110 Digital System Design

ECE 4110–5110 Digital System Design

Dataflow Style Combinational Design with VHDL

ECE 4110–5110 Digital System Design

CHAPTER 17 VHDL FOR SEQUENTIAL LOGIC

ECE 4110–5110 Digital System Design

IAS 0600 Digital Systems Design

ECE 434 Advanced Digital System L08

Data Flow Modeling of Combinational Logic

Concurrent vs Sequential

VHDL Introduction.

ECE 331 – Digital System Design

EEL4712 Digital Design (VHDL Tutorial).

Presentation transcript:

Lecture #10 Page 1 Lecture #10 Agenda 1.VHDL : Concurrent Signal Assignments 2.Decoders using Structural VHDL Announcements 1.HW #4 due 2.HW #5 assigned ECE 4110– Sequential Logic Design

Lecture #10 Page 2 Concurrent Signal Assignments Concurrency - the way that our designs are simulated is important in modeling real HW behavior - components are executed concurrently (i.e., at the same time) - VHDL gives us another method to describe concurrent logic behavior called "Concurrent Signal Assignments" - we simply list our signal assignments (<=) after the "begin" statement in the architecture - each time any signal on the Right Hand Side (RHS) of the expression changes, the Left Hand Side (LHS) of the assignment is updated. - operators can be included (and, or, +, …)

Lecture #10 Page 3 Concurrent Signal Assignments Concurrent Signal Assignment Example entity TOP is port (A,B,C : inSTD_LOGIC; X : outSTD_LOGIC); end entity TOP; architecture TOP_arch of TOP is signal node1 :STD_LOGIC; begin node1<= A xor B; X <= node1 or C; end architecture TOP_arch; node1

Lecture #10 Page 4 Concurrent Signal Assignments Concurrent Signal Assignment Example node1<= A xor B; X <= node1 or C; - if these are executed concurrently, does it model the real behavior of this circuit? Yes, that is how these gates operate. We can see that there may be timing that needs to be considered…. - When does C get to the OR gate relative to (A  B)? - Could this cause a glitch on X? What about a delay in the actual value? node1

Lecture #10 Page 5 Conditional Signal Assignments Conditional Signal Assignments - we can also include conditional situations in a concurrent assignment - the keywords for these are: "when"= if the condition is TRUE, make this assignment "else" = if the condition is FALSE, make this assignment ex)X <= '1' when A='0' else '0'; Y <= '0' when A='0' and C='0' else '1'; - X and Y are evaluated concurrently !!! - notice that we are assigning static values (0 and 1), this is essentially a "Truth Table" - if using this notation, make sure to include every possible input condition, or else you haven't described the full operation of the circuit.

Lecture #10 Page 6 Conditional Signal Assignments Conditional Signal Assignments - We can also assign signals to other signals using conditions - this is similar to a MUX ex)X <= A when Sel='0' else B; - Again, make sure to include every possible input condition, or else you haven't described the full operation of the circuit. - If you try to synthesis an incomplete description, the tool will start making stuff up!

Lecture #10 Page 7 Selected Signal Assignments Selected Signal Assignment - We can also use a technique that allows the listing of "choices" and "assignments" in a comma delimited fashion. - this is called "Selected Signal Assignment" but it is still CONCURRENTLY assigned syntax: with expression select signal-name <= signal-value when choices, signal-value when choices, : signal-value when others; - we use the term "others" to describe any input condition that isn't explicitly described. Note the difference between, and ;

Lecture #10 Page 8 Selected Signal Assignments Selected Signal Assignment Example Describe the following Truth Table using Selected Signal Assignments: Input X begin with Input select X<= '0' when "000", '1' when "001", '1' when "010", '0' when "011", '1' when "100", '1' when "101", '0' when "110", '0' when "111";

Lecture #10 Page 9 Selected Signal Assignments Selected Signal Assignment Example - we can shorten the description by using "others" for the 0's - we can also use "|" delimited choices Input X begin with Input select X<= '1' when "001" | "010" | "100" | "101", '0' when others;

Lecture #10 Page 10 Decoders using Structural VHDL Decoders - a decoder has n inputs and 2 n outputs - one and only one output is asserted for a given input combination ex) truth table of decoder Input Output these are key circuits for a Address Decoders

Lecture #10 Page 11 Decoders using Structural VHDL Decoder Structure - The output stage of a decoder can be constructed using AND gates - Inverters are needed to give the appropriate code to each AND gate - Using AND/INV structure, we need: 2 n AND gates n Inverters Showing more inverters than necessary to illustrate concept

Lecture #10 Page 12 Decoders using Structural VHDL Decoders with ENABLES - An Enable line can be fed into the AND gate - The AND gate now needs (n+1) inputs - Using positive logic: EN = 0, Output = 0 EN =1, Output depends on input code