SKIROC ADC measurements and cyclic ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting Orsay June 2008

02/06/2008 Reminder: one channel of SKIROC 2 ADC LPC ADC LAL Mux  Two ramp ADC: one from LAL, one from LPC  Resolution of 12 bits,  Mux. to select data output with slow control  Power pulsing implemented on ADC ADC LAL

02/06/2008 Setup of test LPC 3 ADC LPC ADC LAL Mux Main difference with LAL setup: external reference ADC to acquire the analog probe signal SKIROC test board Reference ADC board

02/06/2008 Setup of test LPC 4 ADC LPC ADC LAL Mux  Use of an external ADC to acquire the input of Skiroc ADC through the analog probe  Automatic test with a single PC to control via 3 USB ports:  SKIROC  the pulse generator  The reference ADC With a linear probe buffer & ADC AD7684 Function transfer of ADC under test: F ADC = Dski(Vin)/Dref (Vin)

02/06/2008 Simulated linearity of the probe buffer Non-Linearity error within  500µV up to 1.4V In simulation, no significant non-linearity introduced by the probe buffer 5

02/06/2008 Pedestal measurements 6 ADC LPC ADC LAL Mux SKIROC test board ADC LAL ADC LPC without ch# 3,5,33,34 ADC LAL 4 no-functional channels  9 mV  23 mV  Pedestal dispersion mainly due to comparator offsets  Latest version comparator LPC has offset dispersion lower than 5mV (standard deviation) ½ full dynamic range (≈ 2000 ADC counts) Offset of ≈ 1000 ADC counts

02/06/2008 Noise measurements 7 ADC LAL ADC LPC No input signal 0.7V input pulse voltage 150 ADC counts 30 ADC counts 13 ADC counts 200 measurements

02/06/2008 Linearity measurements 8 ADC LAL Channel 1 Channel 18 Channel 36 Red: ADC LAL Blue: ADC LPC  200 steps from 0 to 1.1V, mean value of 10 meas./step  Non-Linearity within  5LSB up to ≈0.8V  Nearly similar curves for the 2 ADCs  Linearity performance limited by the setup of the test ?? 8

02/06/2008 A 12-bit cyclic ADC (1)  A 12-bit cyclic ADC sent to fabrication the 21th of March  Delivery expected this week  ADC designed with the validated building blocks (Amplifier & Comparator) of our 10-bit pipeline ADC (published in IEEE NS in June 08) 9  Advantages of the cyclic architecture:  Small area: (700x250) µm 2  One ADC/channel for the final 64ch. chip  Intrinsic serial output data  Good tradeoff between speed, resolution & consumption

02/06/2008 A 12-bit cyclic ADC (2)  Performance of the designed cyclic ADC:  Optimized architecture w/ 1 ampli. & 4 comp.  Time of conversion: 7µs w/ 1MHz clock freq.  Consumption: 4 mW  Integrated cons. with power pulsing: 0.12 µW  INL within  1.5LSB, and DNL within  1.0 LSB 10 2 conversion phases with a single ampli.

02/06/2008 Conclusion SKIROC measurements:  Test bench in Clermont is now operational (thanks to Mowafak, Francois, LAL)  Preliminary LPC show:  Lower pedestal dispersion for ADC LAL but offset  LAL ADC noisier than LPC one  Similar linearity for both ADC with resolution limited to ≈ 9 bits  Discussion with LAL required :  To compare LAL/LPC results  To understand results (pedestal offset, noise vs amplitude, non-linearity…)  To program complementary meas.  Power pulsing  Improved linearity meas.  … Cyclic ADC:  Our best candidate for the final 64-channels VFE chip  Performance of the 1 st prototype evaluated in June/July 11

02/06/2008 SPARE

02/06/2008 Linearity measurements 13 ADC LAL ADC LPC

02/06/2008 Reminder: one channel of SKIROC 14 ADC LAL ADC LPC