Performed By: Tal Goihman & Irit Kaufman Instructor: Mony Orbach Bi-semesterial Spring /04/2011

Introduction  Goal: implement a fast A/D sampler up to 5Gsps.  Input options: Single 5Gsps Dual 2.5Gsps Quad 1.25Gsps  Output - Sampled data available on: ML605 On-board DDR3 PC Memory & file system - through PCI-E

Hardware Components A/D Sampler (FMC125) Virtex6 Development Board (ML605) PC

Simplified Block Diagram A/D Sampler Memory Controller DDR3 PCI-E Controller PC Application Semester A Semester B

A/D Sampler The FMC125 is a Quad-Channel ADC that provides four 8-bit ADC channels enabling simultaneous sampling of 1, 2, or 4 5, 2.5, 1.25Gsps respectively.  Controlled via SPI.  Uses the EV8AQ160 chip from e2vEV8AQ160  Features: Selectable analog input range (500mVpp / 625mVpp) Selectable input bandwidth (0.5, 0.6, 1.5, 2 GHz) Individual Gain, Offset & Phase controls > 60dB channel isolation

Memory Controller & Memory  Standard Xilinx MIG implementation for DDR3 Memory Controller.  Performance (on ML605) 800 MT/s 64-bit wide interface = 6.25 GB/s theoretical throughput  ML605 comes with a 512MB DDR3 SODIMM, Expandable up to a 2GB module

PCI-Express Block  Xilinx IP available  ML605 can be connected to a PC using PCI-E as: 8 lane PCI-E Gen1 (250MB/sec/lane) 4 lane PCI-E Gen2 (500MB/sec/lane) Both operate at maximum 2GB/s total  Implemented at Part 2 of the project.

PC software Block  Read sampled data from PCI-E to memory and disk.  Control Sampling Start / Stop.  Control some system parameters Configuration of A/D channels Sample rate Sampled data size …  Implemented at Part 2 of the project.

Sampling process All Data is read from memory and transferred to PC via PCI-E Data is sampled & written to memory until the memory is filled.

Timeline WW 15 MIG Familiarization / study WW MIG functionality demonstration WW 18 FMC125 Familiarization / study WW FMC125 functionality demonstration WW 21 Middle of semester presentation

Backup  Documantaion Documantaion