A 1.2V 26mW Configurable Multiuser Mobile MIMO-OFDM/-OFDMA Baseband Processor Motivations –Most are single user, SISO, downlink OFDM solutions –Training or subcarrier allocation dependent multiuser frequency synchronization –Conventional ICI/MAI cancellation is computational intensive Targets –Communication SoC –Multiuser solution –High performance/ low complexity ICI/MAI cancellation –Power efficient processor –Mobility Base-Station

Architecture of the Proposed Receiver Buffer scheduling for memory reduction Taylor series expansion for MUL reduction New algorithm for joint ICI/MAI cancel. and CFO est. design Parallel processing for output latency improvement

Implementation Results 2 orders BER and MSE improvement2 orders BER and MSE improvement 78% hardware reduction in ICI/MAI cancellation78% hardware reduction in ICI/MAI cancellation Power efficient (2.31 Mbps/mW) ASIC implementationPower efficient (2.31 Mbps/mW) ASIC implementation Technology0.13 mm CMOS Area (mm 2 ) Chip3.34 x 3.34 Core2.28 x 2.28 Supply Voltage1.2 V Logic Gates570 K SRAMs58 Kb Clock Rate45 MHz Throughput60 Mbps Power Consumption26 mW Chip Micrograph Chip Summary SoC Integration