Evaluating and Optimizing IP Lookup on Many Core Processors Author: Peng He, Hongtao Guan, Gaogang Xie and Kav´e Salamatian Publisher: International Conference on Computer Communication Networks Presenter: Yu Hao, Tzeng Date: 2012/12/05 1

Outline Introdution DIR-24-8-BASIC Background IP Lookup on TILEPro64 Performance Evaluation Hybrid IP Lookup Scheme Conclusion 2

Introdution Implement IP lookup algorithms in practice on a many-core processor—TILEPro64 Measure the performance of different algorithms on many core chips using different traces Propose a hybrid scheme to combine the strengths of two algorithms (Tree Bitmap and DIR-24-8-BASIC) 3

Introdution (Cont.) DIR-24-8-BASIC TBL24 TBLlong 4

Background The Tree Bitmap algorithm The DIR-24-8-BASIC algorithm The TILEPro64 architecture Produced ： 2008 Common manufacturer ： Tilera Max. CPU clock rate ： 600 MHz to 866 MHz Min. feature size ： 90nm Cores ： 64 5

IP Lookup on TILEPro64 Implementation Tree Bitmap DIR-24-8-BASIC Optimization tricks Large page Initializing an array for trie Counting the number of 1s in a bitmap Lazy checking 6

Performance Evaluation Evaluation Traces Random Match Realistic Random Match Realistic and Filtered 7

Performance Evaluation (Cont.) Evaluation Traces Random Match Leaf push Collect the longest path (Random Match Set) Choose randomly one prefix in the Random Match Set If the prefix is not 32-bit long, we use a random number to complement this prefix into a 32-bit IP address. Realistic Random Match Realistic and Filtered 8

Performance Evaluation (Cont.) Evaluation Traces Random Match Realistic Random Match Define an association array H mapping anonymized addresses to the valid one For any anonymized IP p, if there exists H[p], we replace it with H[p] If not, we generate a valid IP address q using the method described in random match and we replace p with q, and let H[p] = q. Realistic and Filtered 9

Performance Evaluation (Cont.) Evaluation Traces Random Match Realistic Random Match Realistic and Filtered Filter out all valid IP addresses 10

Performance Evaluation (Cont.) Evaluation Traces Random Match Realistic Random Match Realistic and Filtered 11

Performance Evaluation (Cont.) Single-core Performance Evaluations MB 2.9MB 4MB

Performance Evaluation (Cont.) Pipeline Parallel Performance Evaluations 13

Performance Evaluation (Cont.) Run-to-complete Parallel Performance Evaluations DIR-24-8-BASIC 14

Performance Evaluation (Cont.) Run-to-complete Parallel Performance Evaluations TBP

Performance Evaluation (Cont.) Run-to-complete Parallel Performance Evaluations TBP

Hybrid IP Lookup Scheme The DIR-24-8-BASIC runs faster than Tree Bitmap on average. The DIR-24-8-BASIC suffers from a high update overhead. Propose a hybrid IP lookup scheme to combine the strength of both 17

Hybrid IP Lookup Scheme (Cont.) Basic idea Store the short prefixes of length 1 to 16 in a Tree Bitmap trie Store the prefixes of length 17 to 24 in the Table TBL24 For the prefixes of length 25 to 32, we use only one entry in Table TBL24 to store a pointer and put the remaining 8- bit in a sub-trie. 18

Hybrid IP Lookup Scheme (Cont.) Lookup process We first perform the long prefix lookup ( > /16) using Table TBL24 and the attached sub-tries. If there are not any prefixes matching this IP address, we perform the lookup process on the independent Tree Bitmap trie which store the short prefixes. 19

Hybrid IP Lookup Scheme (Cont.) Performance 20

Conclusion Compared to the work of PacketShader which uses GPUs to do the IP lookup, the power consumption of our solution is much lower. The run-to-complete model is more suitable on many core chips. A new hybrid IP lookup scheme which provides a low bound to the worst case update overhead for DIR-24-8-BASIC 21