MODULE 5 INTEL 8086

TODAY WE ARE GOING TO DISCUSS ABOUT, FEATURES OF 8086 LOGICAL PIN DIAGRAM INTERNAL ARCHITECTURE REGISTERS AND FLAGS OPERATING MODES PHYSICAL ADDRESS GENERATIONS MEMORY SEGMENTATION

TODAY WE ARE GOING TO DISCUSS ABOUT, FEATURES OF 8086 LOGICAL PIN DIAGRAM INTERNAL ARCHITECTURE REGISTERS AND FLAGS OPERATING MODES PHYSICAL ADDRESS GENERATIONS MEMORY SEGMENTATION

FEATURES OF 8086 MICROPROCESSOR  1) 8086 has 16-bit ALU  2) It has 16-bit data bus, so it can read data or write data to memory or I/O ports either 16 bits or 8 bits at a time.  3) It has 20 address lines, so it can address up to 2 20 i.e = 1Mbytes of memory  4) 8086 includes few features, which enhance multiprocessing capability (it can be used with math coprocessors like 8087, I/O processor 8089 etc.  5) Operates on +5v supply and single phase (single line) clock frequency.(Clock is generated by separate peripheral chip 8284).

FEATURES CONTINUED … 66 ) 8086 comes with different versions runs at 5 MHz, runs at 8 MHz, runs at 10 MHz. 77 ) It comes in 40-pin configuration with HMOS technology having around 20,000 transistors in its circuitry. 88 ) It has multiplexed address and data bus like 8085 due to which the pin count is reduced considerably 99 ) Higher Throughput (Speed)(This is achieved by a concept called pipelining) FF etching the next instruction while current instruction is under execution is called pipelining.

LOGICAL PIN DIAGRAM INTERNAL ARCHITECTURE REGISTERS AND FLAGS OPERATING MODES PHYSICAL ADDRESS GENERATIONS MEMORY SEGMENTATION ADDRESSING MODES

8086 PIN OUT 7

INTERNAL ARCHITECTURE REGISTERS AND FLAGS OPERATING MODES PHYSICAL ADDRESS GENERATIONS MEMORY SEGMENTATION

Intel 8086

 Execution Unit tells the BIU where to fetch instructions or data from, decodes the instructions and execute the instructions  Bus Interface Unit fetches instructions, read and write data from memory and i/o ports

Intel 8086

REGISTERS AND FLAGS OPERATING MODES PHYSICAL ADDRESS GENERATIONS MEMORY SEGMENTATION

REGISTERS OF THE /2002 JNM

REGISTER ORGANISATION OF 8086

GENERAL PURPOSE REGISTERS 1/2002 JNM AX BX DX CX AH AL 7 0 AX 15 0

GENERAL PURPOSE REGISTERS AX (Accumulator) – favored by CPU for arithmetic operations BX – Base – can hold the address of a variable (SI, DI, and BP can also). Can also perform arithmetic and data movement. CX – acts as a counter for repeating or looping instructions. DX – holds the high 16 bits of the product in multiply (also handles divide operations) 1/2002 JNM

SEGMENT REGISTERS 1/2002 JNM CS SS ES DS CS 15 0

SEGMENT REGISTERS Used as base locations for program instructions, data and the stack CS – Code Segment – holds base location for all executable instructions in a program SS - Base location of the stack DS – Data Segment – default base location for variables ES – Extra Segment – additional base location for memory variables.

1/2002 JNM BP SP DI BP 15 0 SI INDEX REGISTERS

Contain the offset of data(variables, labels) and instructions from its base segment. BP – Base Pointer – contains an assumed offset from the SS register. Often used by a subroutine to locate variables that were passed on the stack by a calling program. SP – Stack Pointer – Contains the offset of the top of the stack. 1/2002 JNM INDEX REGISTERS

Speed up processing of strings, arrays, and other data structures containing multiple elements. SI – Source Index – Used in string movement instructions. The source string is pointed to by the SI register. DI – Destination Index – acts as the destination for string movement instructions 1/2002 JNM

1/2002 JNM IP Flags IP 15 0 STATUS AND CONTROL REGISTERS

IP – Instruction Pointer – contains the offset of the next instruction to be executed. Flags Register – individual bit positions within register show status of CPU or results of arithmetic operations. Control Flags (Direction, Interrupt, Trap) Status Flags (Carry, Overflow, Sign, Zero, Auxiliary Carry, Parity)

FLAG REGISTER IN 8086

PHYSICAL ADDRESS GENERATIONS MEMORY SEGMENTATION OPERATING MODES

ABSOLUTE ADDRESS CALCULATION Addresses can be interpreted in 2 formats: 32-bit segment-offset address Combines a base location (segment) with an offset to represent a logical location (I.E. 08F1:0100) 20-bit absolute address (8086/88 has 20-bit address bus -> 1,048,576 different addresses) Refers to a physical address (09010) 1/2002 JNM

CALCULATION OF PHYSICAL ADDRESS Use segment value: 08F1 08F1 = Multiply by 10 08F1 x10 = 08F10 Add the offset value: F =  Physical Address = /2002 JNM

GENERATION OF 20 BIT PHYSICAL ADDRESS The 20-bit Physical address is often represented as: Segment Base : Offset OR CS : IP CS  Implied Zero (from shft Left) +IP A3 4 H

MEMORY SEGMENTATION OPERATING MODES

MEMORY SEGMENTATION

The memory in an 8086/8088 based system is organised as segmented memory. The complete physically available memory may be divided into a number of logical segments. Each segment is 64K bytes in size and is addressed by one of the segment registers. The 16-bit contents of the segment register actually point to the starting location of a particular segment. To address a specific memory location within a segment, we need an offset address. T he offset address is also 16-bit long so that the maximum offset value can be FFFFH, and the maximum size of any segment is thus 64K locations. MEMORY SEGMENTATION

ADVANTAGES OF MEMORY SEGMENTATION  Allow the memory capacity to be 1Mb even though the addresses associated with the individual instructions are only 16 bits wide.  Facilitate the use of separate memory areas for the program, its data and the stack.  Permit a program and/or its data to be put into different areas of memory each time the program is executed.  Multitasking becomes easy.

OPERATING MODES

MINIMUM MODE

Mode is determined by mn/mx pin Minimum mode also called as uni micro processor system Itself generate all control signals

8086 PIN OUT 36

MAXIMUM MODE

8086 PIN OUT 38

MAXIMUM MODE Mode is determined by mn/mx pin In maximum mode 8086 can work with 8087 External bus controller 8288 required to generate bus control signals

TODAY, WHAT WE ARE DISCUSSED FEATURES OF 8086 LOGICAL PIN DIAGRAM INTERNAL ARCHITECTURE REGISTERS AND FLAGS OPERATING MODES PHYSICAL ADDRESS GENERATIONS MEMORY SEGMENTATION

I will give notes for fifth module, (printed ) tomorrow itself…!!!