Anshul Kumar, CSE IITD CSL718 : Memory Hierarchy Cache Memories - continued 13th Feb, 2006

Anshul Kumar, CSE IITD slide 2 Cache Policies Placement/Mapping –Direct, Associative, Set associative, Sector mapped Read –Sequential / Concurrent, Simple / Forward Load –Block load / Load forward / Wrap around Fetch –Demand fetch, Software pre-fetch, Hardware pre-fetch Replacement –LRU / LFU / FIFO / Random

Anshul Kumar, CSE IITD slide 3 Fetch Policies Demand fetching –fetch only when required (miss) Hardware prefetching –automatically prefetch next block Software prefetching –programmer decides to prefetch questions: –how much ahead (prefetch distance) –how often

Anshul Kumar, CSE IITD slide 4 Software Control of Cache Software visible cache –mode selection (WT, WB etc) –block flush –block invalidate –block prefetch

Anshul Kumar, CSE IITD slide 5 Replacement Policies Least Recently Used (LRU) Least Frequently Used (LFU) First In First Out (FIFO) Random

Anshul Kumar, CSE IITD slide 6 Write Policies Write Hit –Write Back –Write Through Write Miss –Write Back –Write Through With Write Allocate With No Write Allocate

Anshul Kumar, CSE IITD slide 7 Write Policies Write Back (WB) Write Through (WT) Write into memory later No consistence Higher block traffic No word traffic Better for larger cache/ low miss rate Write into memory now Consistence maintained Reduced block traffic Word traffic introduced Better for smaller cache/ higher miss rate

Anshul Kumar, CSE IITD slide 8 Looking deeper : Write Hit Write Through (WT) Write in cache+mem Write Back (WB) Write in cache only Write in mem only Does not make sense

Anshul Kumar, CSE IITD slide 9 Looking deeper : Write Miss Write Back (WB) Does not make sense Allocate missing block and write in cache Write in mem yesno yes Write Through Write Allocate (WTWA) Write Through No Write Allocate (WTNWA)

Anshul Kumar, CSE IITD slide 10 Write Policies : Common combinations     Write Miss Write Hit WBWTWA WT WB WTNWA

Anshul Kumar, CSE IITD slide 11 Write Policies: Timings Timings as seen on the bus –depends on the amount of data transferred (number of blocks and/or words) Timings as seen by the CPU –can be minimized by using a buffer

Anshul Kumar, CSE IITD slide 12 Write Policies : Bus times in Write Hit TwTw 0 TwTw 00 TwTw Write Miss Write Hit WBWTWA WT WB WTNWA

Anshul Kumar, CSE IITD slide 13 Write Policies : Bus times in Read Miss T b (1-P c ) TbTb TbTb Write Miss Write Hit WBWTWA WT WB WTNWA T b +

Anshul Kumar, CSE IITD slide 14 Write Policies : Bus times in Write Miss T b (1-P c ) T b + T b (1-P c ) Write Miss Write Hit WBWTWA WT WB WTNWA T b + TwTw TwTw TwTw TwTw

Analyzing Write Policies:CPU time Hit:WB, Miss: WB1T b + i11 Hit:WB, Miss: WTWA1T b + i11 Hit:WB, Miss: WTNWA1T b + i11 Hit:WT, Miss: WB1T b + i11 Hit:WT, Miss: WTWA1T b + i11 Hit:WT, Miss: WTNWA1T b + i11 PolicyReadReadWriteWrite hitmisshitmiss i depends on read policy

Anshul Kumar, CSE IITD slide 16 Analyzing Write Policies:Bus time Hit:WB, Miss: WB0T b (2-Pc)0 T b (2-Pc) Hit:WB, Miss: WTWA0T b (2-Pc) 0 T b (2-Pc)+T w Hit:WB, Miss: WTNWA0T b (2-Pc) 0 T w Hit:WT, Miss: WB0T b (2-Pc) T w T b (2-Pc) Hit:WT, Miss: WTWA0T b T w T b +T w Hit:WT, Miss: WTNWA0T b T w T w PolicyReadReadWriteWrite hitmisshitmiss

Anshul Kumar, CSE IITD slide 17 More Choices for Write Miss-WT Fetch on Write Write Around Does not make sense Fetch on Write Write Allocate yesno yes Write Validate T b + T w  T w

Anshul Kumar, CSE IITD slide 18 More Choices for Write Miss-WT Fetch on Write Write Around Does not make sense Fetch on Write Write Allocate yesno yes Write Validate Write before hit no yes no yes Rewrite (cache) Write invalidate Direct mapped cache

Anshul Kumar, CSE IITD slide 19 Write Miss-WT Choices (no write before hit) Allocate a block in cache Fetch contents from mem Write word in cache Write word in mem Write Allocate, Fetch on Write Write word in mem only No Write Allocate, No Fetch on Write Allocate a block in cache, mark all invalid Write word in cache, mark it valid Write word in mem Write Allocate, No Fetch on Write

Anshul Kumar, CSE IITD slide 20 Write Miss-WT Choices (write before hit) Allocate a block in cache Fetch contents from mem Re-write word in cache Write word in mem Write Allocate, Fetch on Write Invalidate word in cache, write in mem No Write Allocate, No Fetch on Write Allocate a block in cache, mark all invalid Re-write word in cache, mark it valid Write word in mem Write Allocate, No Fetch on Write