1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 6 Report Wednesday 6 th August 2008 Jack Hickish

2 Progress Last Week Implemented SPI – leaving 12 free connections between USB controller and FPGA Integrated ability to output error flags from FPGA – yet to see working from user interface Extended downscaling (sampling/averaging) capabilities, encountering problems with limited FPGA resources

3 Since then... Downscaling Having experimented to determine the resource use of different components, the downscaling capability of the ADC has been reduced to a ratio of 2 19 giving a minimum data output of around 5 samples per second. This reduction has allowed to internal FIFO to be expanded to 16kb (previously 1k) to reduce the speed demands of the USB and any PC based data acquisition software.

4 Error Checking Error Flags PC USB interface now able to read back error flags from FPGA. Flags included: Internal FIFO full/empty flags External FIFO full/empty flags RAM full/empty flags USB full flag Burst/Continuous operation flag 2 bytes output give: - current state of flags - historical state of flags (any flags that went high since last reset)‏

5 Error Checking Error Flags Running continuous mode at full speed gives errors as expected. Running continuous at very low speed (1 channel, 512 averaging) gives no errors, as expected. but... This simple error checking system becomes problematic when used in continuous mode at all but the lowest speeds. FPGA must receive stop command as soon as PC stops taking data – otherwise FIFO overflows very rapidly. Stop command itself takes a relatively long time to send (16 bits in serial taking time to send a write pulse for each bit) – in this time FIFO can overflow and flag errors. - New stop command that has own dedicated line between USB controller and FPGA – single line that is raised to 1 to stop acquisition. This faster system may solve or at the very least improve this problem

6 Error Checking (Continuous Mode)‏ The problems encountered when using the SPI bus to output error flag states in continuous mode were not unforeseen – the system was mainly for burst operation. For continuous mode, a more rigorous system has been implemented, that both indicates errors and allows captured data to remain useful. Problems to overcome: - System needs to indicate extent of data loss - System needs to allow data with holes to be correctly assigned to correct channels

7 Solution If the internal FIFO becomes full, a count is kept of how many pieces of data have been lost. When there is once again space in the FIFO, 6 bytes of error information are sent out from the FPGA in the main data stream, before normal operation is resumed. Error Checking (Continuous Mode)‏

8 ADC data is sent out as 14 bits along a 16 bit bus. This leaves 2 bits that can be utilised for error analysis. Implemented system is as follows: b13b10b15b14b11b12b9b8b7b6b5b4b3b0b2b1 b1011b11b12b9b8b7b6b5b4b0b2b1 b1010b11b12b9b8b7b6b5b4b3b0b2b1 b1001b11b12b9b8b7b6b5b4b3b0b2b1 b1000b11b12b9b8b7b6b5b4b3b0b2b1 Data Error1 Error2 Error3 14 bit data Lost data count (bits ) Lost data count (bits ) Lost data count (bits 9 - 0)‏Channel number Error Checking (Continuous Mode)‏

9 This system allows gaps to be identified, and the number of missing pieces of data (up to 38 bit to be recorded)‏ The channel number of the last piece of missing data is also output, allowing data acquisition software to allocate the first piece of data after a gap to the correct channel. (This can be compared with what is expected given the number of pieces of data that have been lost)‏ Error Checking (Continuous Mode)‏

10 Now errors can be identified, the ADC can be tested at various speeds, testing its reliability with different channels and downscaling ratios. Experiments with the ADC will also give some idea of what data acquisition method (multiple data files, single data file written in bursts) will best deal with the continuous data output. The Week Ahead...