OIF 10Gbps Electrical Interfaces Tom Palkert AMCC Supercomm 2003

OIF 10 Gbps Common Electrical Interfaces (CEI)  CEI-SR = Short Reach (0-200mm + one connector) Intended for chip to optical module or chip to chip interfaces 5-6Gbps Gbps  CEI-LR = Long Reach (0-1m + two connectors) Intended for chip to chip interface over a backplane 5-6Gbps Gbps

Future OIF interfaces that could leverage the CEI specifications  SFI = SERDES to Framer  SPI = System Packet Interface  TFI = TDM Fabric Interface

SERDES Framer Interface (SFI) FEC Data OR SERDES Framer Interface (SFI) Data Optical Interface SERDES Device and Optics CEI Common Electrical Interface Status Transmit Link Layer Device Receive Link Layer Device System Packet Interface (SPI) Data Status Data T F I PHY Device TDM Fabric to Framer Interface (TFI) CEI

CEI Common Electrical Interface Data Status Data Status System Packet Interface (SPI) Transmit Interface (SPI) Receive Interface (SPI) SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) Data Transmit Link Layer Device Receive Link Layer Device SERDES Device and Optics FEC Device PHY Device Provide well defined voltage levels and timing budgets

CEI Common Electrical Interface TXREFCK RXREFCK SerdesFramer FEC Processor TXDATA [n:0] RXREFCK RXDATA [n:0] Deskew required to align data channels TXDSC S y s t e m t o O p t i c s O p t i c s t o S y s t e m

CEI-SR Common Electrical Interface Data Status Data Status System Packet Interface (SPI) Transmit Interface (SPI) Receive Interface (SPI) SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) Data Transmit Link Layer Device Receive Link Layer Device SERDES Device and Optics FEC Device PHY Device Capable of driving at least 8 inches/200mm of FR4 with 1 connector 8“ 8"

CEI-LR Common Electrical Interface Data Status TDM Fabric Interface (TFI) SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) Data SERDES Device and Optics FEC Device PHY Device Capable of driving at least 1m of backplane with 1 or 2 connectors 1m8" T F I

CEI Common Electrical Interface Jitter : Phase variations in a signal (clock or data). Complement True Ideal 0-crossing point Sampling point Ideal 1-crossing point Total Jitter is composed of both deterministic and random content.

OIF Common Electrical Interface for Short Reach applications

System Reference Model, OIF-SFI-4 phase 1 implementation agreement OIF-SFI-4 phase 1 Electrical Interface 16 LVDS data lanes and clocks for a bi-directional, 10 Gb/s interface S y s t e m t o O p t i c s O p t i c s t o S y s t e m Serdes REFCLK Framer FEC Processor TXCLK TXDATA [15:0] DC TXCLKSRC AB RXCLK RXDATA [15:0] AB TXCLKSRC AB RXCLK RXDATA [15:0] A B TXCLK TXDATA [15:0] DC

SerdesFramer FEC Processor REFCLK TXCLKSRC AB AB OIF-SFI-4 phase 1  OIF-SFI-4 phase 2 S y s t e m t o O p t i c s O p t i c s t o S y s t e m TXCLK TXDATA [15:0] DC Phase 1 TXDATA [3:0] DC Phase 2 TXCLK TXDATA [15:0] DC Phase 1 TXDATA [3:0] DC Phase 2 RXCLK RXDATA [15:0] A B Phase 1 RXDATA [3:0] AB Phase 2 RXCLK RXDATA [15:0] AB Phase 1 RXDATA [3:0] AB Phase 2

Capable of driving at least 8”/200mm of FR4 interconnect with one connector Possible OIF-SFI-4 phase 3 Interface S y s t e m t o O p t i c s O p t i c s t o S y s t e m Serdes REFCLK Framer FEC Processor TXDATA [1] RXDATA [1] TXDATA [1] 8“/200mm

SerdesFramer FEC Processor Support for an aggregate, Gb/s, bi-directional throughput such as 10 GbE, SONET OC-192 and other systems, including FEC overhead. Possible OIF-SFI-4 phase 3 Interface S y s t e m t o O p t i c s O p t i c s t o S y s t e m TXDATA [1] RXDATA [1] TXDATA [1] REFCK OC GbE FEC

Possible SFI-5 phase 2 Interface (OC-768 SERDES to Framer) using CEI-SR

Possible SFI-5 phase 2 OC-768 SERDES to Framer Interface using CEI-SR TXREFCK RXREFCK Serdes Framer FEC Processor TXDATA [3:0] RXREFCK RXDATA [3:0] SONET OC-768 SDH STM-256 OTN OTU-3 S y s t e m t o O p t i c s O p t i c s t o S y s t e m

Possible SFI-5 phase 2 OC-768 SERDES to Framer Interface using CEI-SR TXREFCK RXREFCK SerdesFramer FEC Processor TXDATA [3:0] RXREFCK RXDATA [3:0] Supports 8”/200mm of FR4 interconnect with one connector 8“/200mm S y s t e m t o O p t i c s O p t i c s t o S y s t e m

SFI-5 OC-768 SERDES to Framer Interface TXREFCK RXREFCK SerdesFramer FEC Processor TXDATA [3:0] TXDATA [15:0] RXREFCK RXDATA [3:0] Supports Forward Error Correction (FEC). EFEC GFEC S y s t e m t o O p t i c s O p t i c s t o S y s t e m RXDATA [3:0]

Possible SFI-5 phase 2 OC-768 SERDES to Framer Interface using CEI-SR TXREFCK RXREFCK SerdesFramer FEC Processor RXREFCK RXDATA [3:0] 4-bit wide data bus DATA [3:0] Gbps DATA [3:0] Gbps S y s t e m t o O p t i c s O p t i c s t o S y s t e m TXDATA [3:0]

TFI TDM Fabric to Framer Interface

Reference Diagram TDM Switch Fabric SONET Framer TFI SONET Framer FEC Processor SONET/SDH OC 3/12/48/192/768 G.709 OTN OTM 1/2/3 10GE LAN PH Processor 10GE LAN PHY SONET Signals Non-SONET Signals SONET Framer

TFI Requirements TDM Switch Fabric SONET Framer TFI SONET Framer FEC Processor 10GE LAN PH Processor SONET Signals Non-SONET Signals SONET Framer SONET/SDH OC 3/12/48/192/768 G.709 OTN OTM 1/2/3 10GE LAN PHY

Possible TFI-5 phase 2 Interface based on CEI (cont.) TDM Switch Fabric SONET Framer TFI-5 SONET Framer FEC Processor SONET/SDH OC 3/12/48/192/768 G.709 OTN OTM 1/2/3 10GE LAN PH Processor 10GE LAN PHY SONET Signals Non-SONET Signals SONET Framer Support lane bandwidths of Gb/s Supports de-skew between lanes Capable of driving at least 1m of Printed Circuit Board with 2 connectors for intra-shelf environments