An optimization of the SAFER+ algorithm for custom hardware and TMS320C6x DSP implementation. By: Sachin Garg Vikas Sharma

Motivation SAFER SoftwareHardware FPGACustom  Function can be implemented on different platform  Each platform has its own implementation & optimization issues We explore these issues by implementing SAFER+ (An Encryption standard) on different platform

SAFER+ (Secure And Fast Encryption Routine) A n introduction Encryption Structure  SAFER+ processes in blocks of 16 Bytes  SAFER+ can have a key length of 128, 192 or 256 bits  Can have 8, 12 or 16 number of rounds respectively  Each round uses two 16-Byte sub keys.

FPGA-Implementation  Resource usage = 13%  Used as a Bench Mark implementation  Max.Freq.=43MHz

Custom(cell based) Implementation 1.Synopsys Design compiler used 2.Retiming and Pipelining driven synthesis 3. Commands used  optimize_design  pipeline_design  balance_register Result Freq= 262 MHz

Software implementation on TMS320C64x Algorithm implemented in C Current results

Summary Tasks Accomplished  Bench mark design implemented on FPGA (43 MHz)  Synthesized & optimized the design using DC and did standard cell based layout and achieved 4X improvement in performance (262 MHz).  Implementation in C for TMS320C64x DSP core Ongoing Work  Further optimization of C code for TMS320C64x DSP core And writing report