Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 14, 2011 Gates from Transistors

Previously Simplified models for reasoning about transistor circuits –Zeroth-order –First-order Penn ESE370 Fall DeHon 2

Today How to construct static CMOS gates Penn ESE370 Fall DeHon 3

Outline Circuit understanding (preclass) Static CMOS –Structure –Inverter –Construct gate –Inverting –Cascading Penn ESE370 Fall DeHon 4

What gate? Penn ESE370 Fall DeHon 5

What function? Penn ESE370 Fall DeHon 6

DeMorgan’s Law /f = a + b What is f? Penn ESE370 Fall DeHon 7

What function? Penn ESE370 Fall DeHon 8

Static CMOS Gate Penn ESE370 Fall DeHon 9

Static CMOS Gate Structure Penn ESE370 Fall DeHon 10

Static CMOS Gate Structure Penn ESE370 Fall DeHon 11

Static CMOS Gate Structure Drives rail-to-rail (output is Vdd or Gnd) Inputs connects to gates  load is capacitive Once charge capacitive output, doesn’t use energy –(first order) Output actively driven Penn ESE370 Fall DeHon 12

Inverter Out = /in Penn ESE370 Fall DeHon 13

Inverter Penn ESE370 Fall DeHon 14

Gate Design Example Penn ESE370 Fall DeHon 15

Gate Design Design gate to perform: f=(/a+/b)*/c Penn ESE370 Fall DeHon 16

f=(/a+/b)*/c Strategy: 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall DeHon 17

f=(/a+/b)*/c PMOS Pullup for f? Penn ESE370 Fall DeHon 18

f=(/a+/b)*/c Use DeMorgan’s Law to determine /f. What is /f ? Penn ESE370 Fall DeHon 19

f=(/a+/b)*/c NMOS Pulldown for /f? Penn ESE370 Fall DeHon 20

f=(/a+/b)*/c Penn ESE370 Fall DeHon 21 a c b

Inverting Gate Penn ESE370 Fall DeHon 22

Inverting Stage Each stage of Static CMOS gate is inverting Penn ESE370 Fall DeHon 23

Why not? Penn ESE370 Fall DeHon 24

Source/Drain Reminder Source is: –Most negative terminal NMOS source of the electrons –Most positive terminal PMOS Source of holes Penn ESE370 Fall DeHon 25

Source Drain Annotation Penn ESE370 Fall DeHon 26 S S S S S S D D D D D D

Static CMOS Source/Drains With PMOS on top, NMOS on bottom –PMOS source always at top (near Vdd) –NMOS source always at bottom (near Gnd) Penn ESE370 Fall DeHon 27

Why not buffer? Penn ESE370 Fall DeHon 28 D D S S

Input at 0V Vgs NMOS? Vgs PMOS? Output voltage? Penn ESE370 Fall DeHon 29 D D S S

D D S S Input at Vdd Vgs NMOS? Vgs PMOS? Output voltage? Penn ESE370 Fall DeHon 30

Behavior Roundup VinInitial VoutFinal Vout 0Vout<0.3Vout (unchanged) 0Vout> Vout< Vout>0.7Vout (unchanged) Penn ESE370 Fall DeHon 31

Why not buffer? Output signal not drive to rails One threshold voltage away True any time use PMOS/NMOS on “wrong” side What’s wrong with it not driving to rails? Penn ESE370 Fall DeHon 32

How do we buffer? Penn ESE370 Fall DeHon 33

How implement OR? Penn ESE370 Fall DeHon 34

Cascading Stages Penn ESE370 Fall DeHon 35

Stages Can always cascade “stages” to build more complex gates Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality –but may not be smallest/fastest/least power Penn ESE370 Fall DeHon 36

Implement: f=a*/b Pullup? Pulldown? Penn ESE370 Fall DeHon 37

f=a*/b Penn ESE370 Fall DeHon 38

Admin Friday in Detkin (RCA) Lab –Note homework 1 (due Friday) to design gates before lab –Please read through HW2, Lab1 details –Bring USB drive with you to lab on Friday to store waveforms Penn ESE370 Fall DeHon 39

Big Idea Systematic construction of any gate from transistors 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall DeHon 40