L26 04/18/021 EE Semiconductor Electronics Design Project Spring Lecture 26 --draft-- Professor Ronald L. Carter

L26 04/18/022 Fig 5.10* Simplified ic Class B output stage Q1 (npn) and Q2 (pnp), are a complementary pair   1 =  2 Q1 off if V i < V beOn Q2 off if V i > -V beOn Dead zone: I L = 0 if -V beOn < V i < V beOn I L 

L26 04/18/023 Fig 5.11* Transfer Characteristic of the Class B Stage

L26 04/18/024 Fig 5.13* Class AB output stage. The gummel diodes reduce crossover distortion. For all conditions, I QFB is the mini- mum curr. to for. bias Q 3 and Q 4 I Q > I B1 + I QFB For V i > -V be2, Q1 cond. the est. currents are as shown  I FB I B1 I C1 =  I B1 I C1max ~ (V CC -V cesat )/R L I B1 IiIi ILIL

L26 04/18/025 Fig 5.14* Transfer characteristic of the circuit of Fig 5.13 Q 1 conducting  Q 2 cond. 

L26 04/18/026 I FB I B1 I C2 =  I B2 I C1max ~ (V CC -V cesat )/R L I B1 IiIi ILIL Fig 5.13* Class AB output stage. Q2 conducting For V i < -V be2, Q2 cond. the es- timated currents are as shown 

L26 04/18/027 Fig 5.15* Voltage and current waveforms for Class B output stage (a) Input voltage (b) Output voltage (c) Q 1 collector current (d) Q 2 collector current  max =  (V CC -V CEsat ) 4V CC < 78.6%

L26 04/18/028 Fig 5.16* Load line for one device in a Class B stage, (for this device conducting) Load line for other device conducting P max,RL = V CC 2 /2R L T j -T amb = (I pk V pk /4)*R th, (Note: Both devices dissipate I pk V pk /4)

L26 04/18/029 Fig 5.20a* Simplified schematic of the 741 output stage See Group Project Optimize current, voltage gain, f T Use Cadence to cap. schematic, set bias, etc. and generate outputs Q 17 inverts input -- biased by Q 13B (c.m.)

L26 04/18/0210 Fig 5.20b* 741 incl. Q18 and Q19 Q 18 and Q 19 are biased by Q 13A (a current mirror) Q 14 and Q 20 are biased by R 19 and A Q18,Q19 /A Q14, A Q20 chosen so comp. Q 14 Q 23 drives output as low res follower Q 17 inverter drives Q 23

L26 04/18/0211 Fig 5.21* SPICE- gen. transf. Char. VCC = 15 V, RL = 1k Q 13 sat, so V omax = V CC -VC E13Asat -V be14 Vi < 0  Q 17 inverts V i so V 1 rises so V 2 & V o follow w/Q 23 & Q 14 Vi > 0  Q 17 sat, so V omin = -V CC +V CE17sat -V be23 -V be20 Q 17 inverts V i so V 1 goes < 0 so V 2 & V o follow w/Q 23 & Q 20 sinking thru R L V i (V) V o (V)

L26 04/18/0212 Fig 5.22* All npn Class B output stage

L26 04/18/0213 Fig 5.23* Transfer char of Fig. 5.22

L26 04/18/0214 References * Analysis and design of analog integrated circuits, 4th ed., by Gray, Hurst, Lewis and Meyer, Wiley, New York, ©2001.