EE 5340 Semiconductor Device Theory Lecture 25 – Spring 2011 Professor Ronald L. Carter

©rlc L25-21Apr20112 Ideal 2-terminal MOS capacitor/diode x -x ox 0 SiO 2 silicon substrate V gate V sub conducting gate, area = LW t sub 0 y L

©rlc L25-21Apr20113 MOS surface states** p- substr = n-channel

©rlc L25-21Apr20114 MOS Bands at OSI p-substr = n-channel Fig 10.9* 2q|  p | qpqp x d,max

©rlc L25-21Apr20115 Equivalent circuit for accumulation Accum depth analogous to the accum Debye length = L D,acc = [  V t /(qp s )] 1/2 Accum cap, C’ acc =  Si /L D,acc Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ acc

©rlc L25-21Apr20116 Equivalent circuit for Flat-Band Surface effect analogous to the extr Debye length = L D,extr = [  V t /(qN a )] 1/2 Debye cap, C’ D,extr =  Si /L D,extr Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ D,extr

©rlc L25-21Apr20117 Equivalent circuit for depletion Depl depth given by the usual formula = x depl = [2  Si (V bb )/(qN a )] 1/2 Depl cap, C’ depl =  Si /x depl Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ depl

©rlc L25-21Apr20118 Equivalent circuit above OSI Depl depth given by the maximum depl = x d,max = [2  Si |2  p |/(qN a )] 1/2 Depl cap, C’ d,min =  Si /x d,max Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ d,min

©rlc L25-21Apr20119 Differential charges for low and high freq From Fig 10.27* high freq.

©rlc L25-21Apr Ideal low-freq C-V relationship Fig 10.25*

©rlc L25-21Apr Comparison of low and high freq C-V Fig 10.28*

©rlc L25-21Apr Effect of Q’ ss on the C-V relationship Fig 10.29*

©rlc L25-21Apr Flat band condition (approx. scale) E c,Ox EvEv AlSiO 2 p-Si q(  m -  ox )= 3.15 eV E Fm E Fp EcEc EvEv E Fi q(  ox -  Si )=3.1eV E g,ox ~8eV q  fp = 3.95eV

©rlc L25-21Apr Flat-band parameters for n-channel (p-subst)

©rlc L25-21Apr Flat-band parameters for p-channel (n-subst)

©rlc L25-21Apr Fig 10.15*  ms (V) N B (cm -3 ) Typical  ms values

©rlc L25-21Apr Flat band with oxide charge (approx. scale) EvEv AlSiO 2 p-Si E Fm E c,Ox E g,ox ~8eV E Fp EcEc EvEv E Fi q(  fp -  ox ) q(V ox ) q(  m -  ox ) q(V FB ) V FB = V G -V B, when Si bands are flat ExEx + -

©rlc L25-21Apr Inversion for p-Si V gate >V Th >V FB V gate > V FB V sub = 0 E Ox,x > 0 Acceptors Depl Reg e - e - e - e - e -

©rlc L25-21Apr Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when n s = N a = p po and V G = V Th Assume n s = 0 for V G < V Th Assume x depl = x d,max for V G = V Th and it doesn’t increase for V G > V Th C d,min =  Si /x d,max for V G > V Th Assume n s > 0 for V G > V Th

©rlc L25-21Apr MOS Bands at OSI p-substr = n-channel Fig 10.9* 2q|  p | qpqp x d,max

©rlc L25-21Apr Computing the D.R. W and Q at O.S.I. ExEx E max x

©rlc L25-21Apr Calculation of the threshold cond, V T

©rlc L25-21Apr Equations for V T calculation

©rlc L25-21Apr Fully biased n-MOS capacitor 0 y L VGVG V sub =V B E Ox,x > 0 Acceptors Depl Reg e - e - e - e - e - e - n+ VSVS VDVD p-substrate Channel if V G > V T

©rlc L25-21Apr MOS energy bands at Si surface for n-channel Fig 8.10**

©rlc L25-21Apr Computing the D.R. W and Q at O.S.I. ExEx E max x

©rlc L25-21Apr Q’ d,max and x d,max for biased MOS capacitor Fig 8.11** x d,max (  m)

©rlc L25-21Apr Fully biased n- channel V T calc

©rlc L25-21Apr n-channel V T for V C = V B = 0 Fig 10.20*

©rlc L25-21Apr Fully biased p- channel V T calc

©rlc L25-21Apr p-channel V T for V C = V B = 0 Fig 10.21*

©rlc L25-21Apr n-channel enhancement MOSFET in ohmic region 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat e - e - e - e - e - n+ p-substrate Channel

©rlc L25-21Apr Conductance of inverted channel Q’ n = - C’ Ox (V GC -V T ) n’ s = C’ Ox (V GC -V T )/q, (# inv elect/cm 2 ) The conductivity  n = (n’ s /t) q  n G =  n (Wt/L) = n’ s q  n (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’ s q  n W)

©rlc L25-21Apr Basic I-V relation for MOS channel

©rlc L25-21Apr I-V relation for n-MOS (ohmic reg) IDID V DS V DS,sat I D,sat ohmic non-physical saturated

©rlc L25-21Apr References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986

©rlc L25-21Apr Computing the D.R. W and Q at O.S.I. ExEx E max x