DOLPHIN INTEGRATION Second Review March 26, Use Plan WP 5: Dissemination and implementation Task 5.1: Market evaluation and use planning Use planning in AMI Semiconductor Belgium

DOLPHIN INTEGRATION Second Review March 26, AMIS Use Plan: Outline Highly accurate ADC in ASIC/ASSP ASIC / ASSP market data analysis Trends analogue SoC Technical challenges analogue SoC testing Valorisation potential

DOLPHIN INTEGRATION Second Review March 26, Highly Accurate A/D converter in ASIC Resolution of 15 bit or higher, moderate sample rates Usage in ASIC made realistic by: New A/D architectures, e.g. sigma-delta Design techniques for low power On-chip digital signal processing capable to handle the digital signal

DOLPHIN INTEGRATION Second Review March 26, Highly accurate A/D converter in AMIS Today standard accuracy is 12 bit New sensor interfaces require 16 – 17 bit resolution, e.g. Gyroscope Acceleration sensor Intelligent battery sensor Making the systems more intelligient and autonomous requires more accurate information

DOLPHIN INTEGRATION Second Review March 26, ASIC / ASSP market data analysis

DOLPHIN INTEGRATION Second Review March 26, ASIC / ASSP market data analysis

DOLPHIN INTEGRATION Second Review March 26, ASIC / ASSP market data analysis

DOLPHIN INTEGRATION Second Review March 26, ASIC / ASSP market data analysis

DOLPHIN INTEGRATION Second Review March 26, ASIC / ASSP market data analysis

DOLPHIN INTEGRATION Second Review March 26, ASIC / ASSP market data analysis

DOLPHIN INTEGRATION Second Review March 26, ASIC / ASSP market trends Market ASICASSP Automotive Usages of analog increases Communica- tion Highly integrated products – less # chips ASP pressure, standards Consumer Low power, low cost, high integration ASP pressure, standards Data processing Increased speed and integration ASP pressure, standards industrial Lower volume, usage of analog increase Usages of analog increases

DOLPHIN INTEGRATION Second Review March 26, SoC test: technical challenges SoC era extremely challenging for test Reduce test time while quality level must go up Reduce test development time All internal circuit blocks have to be “observable” to enable design debug Scan, BIST, parallel testing are helpful for logic SoC but not for the analog blocks

DOLPHIN INTEGRATION Second Review March 26, Test cost challenges Test cost equal the processing cost ?? Source: ITRS roadmap

DOLPHIN INTEGRATION Second Review March 26, Model for Valorisation Use of highly accurate A/D converter The served market are the automotive and industrial segments in the analog / mixed-signal ASIC / ASSP market Reference value 2003: 4.1 B.EUR (4.6 B.USD) Use of test techniques The served market is the total analog / mixed- signal ASIC / ASSP market Reference value 2003: 14.3 B.EUR (15.7B.USD) Same market segments for AMIS Belgium business

DOLPHIN INTEGRATION Second Review March 26, Valorisation A/D Converter Case AMIS Europe YEAR MUSD – auto/industr 50 % % IC with accurat ADC MUSD BUSINESS

DOLPHIN INTEGRATION Second Review March 26, Valorisation A/D Converter Case Global business YEAR MUSD – auto/industr 29 % % with accurat ADC MUSD BUSINESS

DOLPHIN INTEGRATION Second Review March 26, Use Plan test techniques AMIS YEAR MUSD – mix signal busn MUSD – mix sign test cost MUSD – gain 10% tst time MUSD – gain 1.5 s tst time GAIN 1: test is 30% manufacturing cost, reduce by 10 % GAIN 2: time to test ADC is 3 sec, reduce by 1.5 sec

DOLPHIN INTEGRATION Second Review March 26, Conclusion valorisation for AMIS-B Growing need for highly accurate ADC AMIS Business affected by 2009 forecasted 16.6 MUSD Use know-how, design methodology & tools, subcontracting High impact of accurate ADC testing on total manufacturing cost Predicted cost saving for 2009 between 6.4 and 10.2 MUSD based on modest gains in test time Cost saving could already start in 2005