Status report 2010/9/24 Atsushi Nukariya. GEMFE2 outline (1) ・ FPGA controls 4 chips. ・ Each chip has 9 channels. ( 8 channels will be used in data acquisition,

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Presentation transcript:

Status report 2010/9/24 Atsushi Nukariya

GEMFE2 outline (1) ・ FPGA controls 4 chips. ・ Each chip has 9 channels. ( 8 channels will be used in data acquisition, and 1 channels will be used in test. )

GEMFE2 outline (2) ・ Integration type charge-amplifier sends signal to latter part. If data acquisition is finished, MOS FET discharge charge of capacitor. ・ ADC and TDC change analog data into digital data and add information of time. ・ Channel has 2 data buffer. Data buffer is FIFO, 23 bits and 10 depth. The reason why 2 data buffer has is speed up. If one side is mode of writing, the other side is mode of reading. ・ 6+1 bits 10MHz counter decides data buffer which is mode of reading. ・ Channel and FIFO selector decides channel and data buffer which reads data.

Data format ・ Data format consists of status ( 4 bit ), coarse time ( 6 bit ), fine time ( 4 bit ) and ADC ( 10 bit ). But this time, status is most important. ・ Status is represented by 3 bits. List of status is as follows. Normal : Each bit is 0. Data was acquired correctly. No exception procedure is needed. FIFO Full : LSB ( Least significant bit ) is 1, but the others are 0. This status means that data is stocked in the 10th depth. If this data is received, status of data which will be received next time is FIFO empty. FIFO Empty : The 2th bit is 0, MSB ( Most significant bit ) is X ( Don’t care ), and LSB is 0. All bits of coarse time, fine time and ADC, are 0. If this status is received, next channel becomes mode of reading, and empty counter is incremented. If empty counter doesn’t become 8, the status of data will be Chip Full. FIFO Busy : MSB is 1, The 2th bit is X and LSB is 0. All bits of coarse time, fine time and ADC, are 0. This status means that data buffer is mode of writing now.

FPGA outline (1) ・ Class diagram of FPGA is on the website. ( This class diagram is made by the former designer. ) ・ The former designer has already created almost parts. This time, connecting D_BUFFER_128x23bit to ControlManager and connecting FIFO_128x8bitx3 to ControlManager and testing these are my works. ・ Explanation of all function of class spends too much time, so I will only explain only important class. ( More details can be seen at my document. )

FPGA outline (2) ・ D_BUFFER_128x23bit consists of 2 data buffer ( FIFO ). It is important to distinguish data buffer on D_BUFFER_128x23bit from data buffer on chip. Data form GEMFE2 is stored here, and is sent to FIFO_128x8bitx3. ・ FIFO_128x8bitx3 consists of 3 data buffer ( FIFO ). Data from D_BUFFER_128x23bit is divided into 8 bits, 8bits, and 7 bits data. If status is Chip Full, 7 bits data will be added 1 bit which value is 1. Finally these data are sent to SiTCP board. ・ ControlManager decides the behavior of FPGA. I designed this part mainly.

Development environment ・ OS : Windows 7 Home Premium 64bit ・ Software : Xilinx Design Suite ISE 12.2

Input data ・ Input data is 20 bits ( Part of data ) which is selected randomly. ・ Sometimes data which status is FIFO Empty ( 0x ) is included. ・ Input data will be sent at decided time. ( Repeat 2 ( Data buffer ) ×4 ( GEMFE2 ) times. ) ・ Input data is as follows. (1) 0x (9) 0x0f8bb7 (17) 0x0e16b8 (25) 0x (33) 0x0e700f (2) 0x08cb33 (10) 0x (18) 0x019d18 (26) 0x08282d (34) 0x (3) 0x0b91aa (11) 0x07d13d (19) 0x0207d1 (27) 0x0a24fa (35) 0x0d0969 (4) 0x0dd155 (12) 0x0e4418 (20) 0x (28) 0x09bdd5 (36) 0x06304c (5) 0x (13) 0x02480f (21) 0x0e4021 (29) 0x (37) 0x02951c (6) 0x (14) 0x0ce236 (22) 0x0cc642 (30) 0x0c1066 (38) 0x0f220c (7) 0x (15) 0x (23) 0x0f12ff (31) 0x04388f (39) 0x (8) 0x0c1178 (16) 0x094fea (24) 0x (32) 0x00963d

Result (1) ・ Wave form is as follows. ・ I confirmed that FIFO_128x8bitx3 can output data. GEMFE2 A In GEMFE2 B In GEMFE2 C In D_BUFFER_128x23bit Output D_BUFFER_128x23bit Write Enable GEMFE2 D In D_BUFFER_128x23bit Read Enable FIFO_128x8bitx3 Output

Result (2) ・ The wave form at around 16ns, around 22ns. ・ ○ represents that 0x was read at twice. But 0x was written at once. ( ○ )

Result (3) ・ The wave form at around 24ns, 29ns. ・ ○ represents that 0x was read more than expected. 0x wasn’t written. ( ○ )

Problems and plan ・ When D_BUFFER_128x23bit gets signal which changes mode, unexpected data is sent. → I can’t understand this phenomena. Delay of signal might be a cause. → Source of delay : ControlManager controls all functions of FPGA. → Software resolve this problem.(?) ・ Next plan is learning network programming, and create my class libraries.